JP2002368606A - Quantization method for digital phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a quantization method for a digital phase-locked loop circuit that provides a quantized signal having small errors, even without the need for a high-speed clock signal. SOLUTION: Phase difference signals Vp1 , Vp2 , outputted from a phase comparator circuit 1, are fed to 1st and 2nd quantization circuits 2, 3, the 1st and 2nd quantization circuits 2, 3 quantize the phase difference signals Vp1 , Vp2 by using quantization clocks Φ1, Φ2, whose phases are deviated by 180 deg. by a delay circuit 7 and an adder 4 sums signals outputted from the 1st and 2nd quantization circuits 2, 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference quantization method performed in a digital phase locked loop (hereinafter, referred to as "PLL") circuit.

[0002]

2. Description of the Related Art As a method of quantizing a phase difference performed in a conventional digital PLL circuit, for example, there is a method shown in FIG. In FIG. 3, a phase comparison circuit 1 detects a phase difference between an external input signal input from an external input terminal Vin and a phase comparison signal divided by a frequency dividing circuit 8.
And a quantization circuit 2 that samples the detected phase difference using a clock of an oscillator 6 that oscillates a quantization clock frequency f and converts it into a digital value. The oscillation output is controlled by the obtained digital value. And a digital voltage controlled oscillation circuit 5.

The operation of the conventional digital phase locked loop PLL circuit will be described.

The external input signal input from the external input terminal Vin is compared with a phase comparison signal obtained by dividing the frequency output from the digital voltage controlled oscillation circuit 5 by the frequency dividing circuit 8 in the phase comparison circuit 1. A phase difference signal Vp corresponding to the phase difference is output. Phase difference signal Vp
Is input to the quantization circuit 2. The quantization circuit 2 performs sampling using the clock of the oscillator 6 that oscillates the sampling clock frequency f, digitizes the obtained data, and outputs the data to the digital voltage control oscillation circuit 5.

The oscillation frequency of the digital voltage controlled oscillation circuit 5 changes according to the digital value obtained by the quantization circuit 2. The digital voltage controlled oscillation circuit 5 changes the oscillation frequency in the direction in which the phase difference signal obtained in the phase comparison circuit 1 becomes smaller, and makes the frequency of the phase difference signal coincide.

FIG. 4 shows a phase difference signal Vp output from the phase comparison circuit 1, sampling at the sampling clock Φ, and a sampling result (ΣΦ) from the quantization circuit 2.
FIG. In this case, the higher the clock frequency used is, the smaller the error caused by quantization becomes, so that a high-speed clock is used.

[0007]

However, according to the conventional method of quantizing a phase difference in a digital PLL circuit, a high-speed clock is used, so that power consumption is increased, and a peripheral circuit such as an oscillation circuit is not used. There is a problem that the cost of the components used in the circuit tends to increase.

Accordingly, it is an object of the present invention to obtain a quantization method with a small error without using a high-speed clock.

[0009]

In order to achieve the above object, the present invention detects a phase difference between an external input signal and a phase comparison signal divided by a frequency dividing circuit and outputs a phase difference signal. A phase comparison circuit, a quantization circuit that samples the phase difference using a quantization clock and converts it into a digital value, and a digital voltage controlled oscillator circuit whose oscillation output is controlled by the digital value. In a digital phase locked loop circuit, the phase difference signal is first and second signals.
Sending to the first and second quantization circuits, shifting the quantization clock by a predetermined phase difference, and outputting from the first and second quantization circuits. And a method for quantizing in a digital phase-locked loop circuit, the method further comprising the step of adding the obtained signals.

[0010] Also, the inputting of the quantization clock includes a step of inputting the quantization clock with a phase shifted by 180 °, and provides a quantization method in a digital phase locked loop circuit. I do.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a digital PLL circuit according to the present invention. In FIG. 1, a phase comparator 1 detects a phase difference between an external input signal input from an external input terminal Vin and a phase comparison signal divided by a frequency divider 8, and the detected phase difference is divided into two. Are sent to the quantization circuit (1) 2 and the quantization circuit (2) 3, and the clock of the oscillator 6 oscillating the clock frequency f for quantization is sampled by the delay circuit 7 with the phase shifted by 180 degrees. It comprises a digital voltage controlled oscillation circuit 5 in which the digital value is added by the adder 4 and the oscillation output is controlled by the value.

The operation of the digital phase locked loop PLL circuit of the present invention will be described.

The external input signal input from the external input terminal Vin is compared in the phase comparison circuit 1 with the phase comparison signal obtained by dividing the frequency output from the digital voltage controlled oscillation circuit 5 by the frequency dividing circuit 8, A phase difference signal Vp corresponding to the phase difference is output. The phase difference signal Vp is divided into two, and a quantization circuit (1) 2 and a quantization circuit (2) 3
Is input to The quantization circuit (1) 2 performs sampling using a clock Φ1 of an oscillator 6 that oscillates a sampling clock frequency f. The quantization circuit (2) 3 performs sampling using the clock Φ2 whose phase is shifted by 180 ° by the delay circuit 7. The results obtained by the quantization circuit (1) 2 and the quantization circuit (2) are added by the adder 4.

The obtained data is converted into a digitally controlled oscillator 5
Output to The oscillation frequency of the digital voltage controlled oscillation circuit 5 changes according to the digital value obtained by the quantization circuit 2. The digital voltage controlled oscillation circuit 5 changes the oscillation frequency in the direction in which the phase difference signal obtained in the phase comparison circuit 1 becomes smaller, and makes the frequency of the phase difference signal coincide.

FIG. 2 shows a phase difference signal Vp1 output from the phase comparison circuit 1 to the quantization circuit (1), a sampling result (ΣΦ1) at the sampling clock φ1, and an output from the phase comparison circuit 1 to the quantization circuit (2). Phase difference signal Vp2, the sampling result (ΣΦ2) at the sampling clock Φ2, and the added output signal (ΣΦ2).
1+ で Φ2).

Here, comparing FIG. 4 showing the conventional example with this figure, the sampling result of the present invention is the same as that of the conventional example even though the sampling interval is longer, that is, the sampling frequency is lower. From this, it can be seen that if the accuracy is the same as the conventional one, the sampling frequency may be halved. Also, if the sampling frequency is the same as the conventional one, the accuracy is doubled.

[0017]

As described above, according to the present invention,
Since the phase difference signal is divided into two and quantized by shifting the phase by 180 degrees, and they are added, a quantization method with a small error can be obtained without using a high-speed quantization clock. Further, a PLL circuit using a quantization circuit having a small error was obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a digital PLL circuit including a quantization method according to the present invention.

FIG. 2 is a diagram showing a phase difference signal, a sampling clock, and a sampling result of the present invention.

FIG. 3 is a diagram showing a conventional digital PLL circuit.

FIG. 4 is a diagram showing a phase difference signal, a sampling clock, and a sampling result of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2 Quantization circuit 3 Quantization circuit 4 Adder 5 Digital voltage controlled oscillation circuit 6 Oscillator 7 Delay circuit 8 Divider circuit

Claims (2)

[Claims] 1. A phase comparison circuit for detecting a phase difference between an external input signal and a phase comparison signal divided by a frequency division circuit and outputting a phase difference signal, and using a clock for quantizing the phase difference. And a digital voltage-controlled oscillating circuit whose oscillation output is controlled by the digital value, wherein the phase difference signal is first and second. Sending to the first and second quantization circuits, shifting the quantization clock by a predetermined phase difference, and outputting from the first and second quantization circuits. Adding a selected signal to the digital phase locked loop circuit. 2. The digital phase locked loop circuit according to claim 1, wherein the step of inputting the quantization clock includes the step of inputting the quantization clock with a phase shifted by 180 °. Quantization method.