JP5133818B2 - Signal reproduction device - Google Patents

Description

  In the present invention, a TS (Transport Stream) signal (TS signal) that is a packetized broadcast data such as a video signal and an audio signal formed based on a compression coding method such as the MPEG (Motion Picture Experts Group) standard is used. The present invention relates to a signal reproduction device that receives a terrestrial digital broadcast signal, and more particularly to a signal reproduction device that reproduces a clock from the received terrestrial digital broadcast signal.

  When broadcasting broadcast program signals consisting of video signals and audio signals are wirelessly transmitted, the analog FM (Frequency Modulation) method has been used in the past, but in recent years the QAM (Quadrature Amplitude Modulation) method has been used. Wireless digital transmission schemes using digital modulation schemes such as OFDM (Orthogonal Frequency Division Multiplex) schemes have come to be used.

  When a broadcast program signal is transmitted (broadcast) to a general household using such a digital transmission method, the digital broadcast program signal (digital data) is sent from a studio to a wireless relay device provided at, for example, Tokyo Tower. STL (Studio to Transmitter Link) and TTL (Transmitter to Transmitter Link) for transmitting digital broadcast program signals between wireless relay devices are used. For STL and TTL digital terrestrial broadcasting in Japan, Broadcast data such as a video signal and an audio signal is transmitted by modulating a packetized TS signal having a transmission bit rate of about 32 Mbps formed based on a compression coding method based on the MPEG standard or the like by the digital modulation method described above. The ISDB-T (Integrated Service Digital Broadcasting-Terrestrial) method is used, but the ARIB (Association of Radio) is also used. According to the standards of Industries and Businesses), a two-wire system that transmits this and an 8 MHz clock is adopted. On the other hand, in most regions except Japan and the United States, a one-wire system that transmits only the TS signal packetized as described above according to the DVB (Digital Video Broadcasting) standard is adopted.

  The ISDB-T system is a system in which one channel is divided into 13 segments (one segment is a frequency band of 429 KHz) in terrestrial digital broadcasting, and one to a plurality of segments can be used according to data to be transmitted. is there. For example, one segment is used for a portable device, four segments are used for a television having a normal image quality, and 12 segments are used for a high-definition television.

  On the other hand, when the broadcasting material acquired at the relay site is transmitted to the studio, it is transmitted from the relay site to the studio via the base station (wireless relay device). Between the wireless relay device and the studio, TSL (Transmitter to Studio Link) wireless transmission line is used, and the above wireless transmission method is used. On the other hand, as a wireless transmission system from a relay site to a wireless relay device, a transmission FPU (Field Pickup Unit) device provided on the relay camera side and a reception FPU device provided on the wireless relay device side are provided. A wireless transmission system (signal reproduction device) is used.

  FIG. 11 is a block diagram showing an example of a conventional TSL radio transmission system using an FPU device, where 100 is a transmission-side FPU (FPU-TX) device, 101 is an interface, 102 is a modulation unit, and 103 is A converter, 104 is a transmission antenna, 105 is a reception antenna, 106 is an FPU (FPU-RX) device on the reception side, 107 is a converter, 108 is a demodulation unit, and 109 is an interface.

  In this figure, this conventional example is based on the ARIB standard, and transmission data DATA-t consisting of video signals and audio signals from a relay camera device (not shown) and a transmission clock CK-t are FPU-TX devices. 100. The FPU-TX device 100 processes transmission data DATA-t having a transmission bit rate of 60 Mbps or 44 Mbps. In this case, the transmission clock CK-t is 44 MHz.

  In the FPU-TX device 100, the 44Mbps transmission data DATA-t and the 44MHz transmission clock CK-t are input from the interface 101. The input transmission data DATA-t is subjected to processing such as energy spread modulation, Reed-Solomon coding, interleaving, convolutional coding, and 64QAM modulation by the modulation unit 102 based on the transmission clock CK-t. Thus, the signal is converted into a microwave band signal and transmitted from the transmitting antenna 104.

  On the other hand, the FPU-RX device 106 on the reception (that is, base station (wireless relay device)) side receives the microwave signal transmitted from the FPU-TX device 100 by the receiving antenna 105, and the converter 107 has the original frequency band. After being converted to the above signal, the demodulator 108 sets the original 44 Mbps data (received data) DATA-r even after processing such as 64QAM demodulation, Viterbi decoding, deinterleaving, Reed-Solomon decoding, and energy despreading modulation, Output from the interface 109. The interface 109 extracts a 44 MHz clock CK-r from the demodulated data DATA-r and outputs it together with the received data DATA-r. The reception data DATA-r and clock CK-r are transmitted to a studio (broadcast station) (not shown) by TSL.

  FIG. 12 is a block diagram showing another example of a conventional TSL radio transmission system using an FPU device, in which 200 is an FPU (FPU-TX) device on the transmission side, and 201 is a serial / parallel conversion / rate converter. , 202 is a modulation unit, 203 is a converter, 204 is a transmission antenna, 205 is a reception antenna, 206 is a receiving FPU (FPU-RX) device, 207 is a converter, 208 is a demodulation unit, and 209 is a parallel / serial conversion / rate. It is a converter.

  In this figure, this conventional example is based on the DVB standard, and serial transmission data DVB-t having a transmission bit rate of 44 Mbps consisting of a video signal and an audio signal from a relay camera device (not shown) is FPU-TX. Supplied to the apparatus 200. In the FPU-TX device 200, the transmission data DVB-t is serial / parallel converted by the serial / parallel conversion / rate converter 201, and at the predetermined transmission bit rate by inserting / deleting additional packets (NULL packets). The signal is converted, further subjected to, for example, OFDM modulation by the modulation unit 202, converted into a microwave signal by the converter 203, and transmitted from the transmission antenna 204.

  On the other hand, in the FPU-RX device 206 on the reception (ie, base station (wireless relay device)) side, the microwave signal transmitted from the FPU-TX device 200 is received by the reception antenna 205, and the original frequency band of the converter 207 is also received. Then, the signal is demodulated by the demodulator 208 and converted to serial data (received data) DVB-r having a transmission bit rate of 44 Mbps by the parallel / serial conversion / rate converter 209 and output.

  By the way, in the broadcast transmission system as described above, if the above STL or TTL is in a defective state, terrestrial digital broadcasting to a general home or the like cannot be performed. As a method for avoiding such a situation, a technique has been proposed in which a signal reproducing device configured by the FPU device described above can be used as an alternative system for such STL or TTL (see, for example, Patent Document 1).

  In the technique described in Patent Document 1, a 32.5 Mbps (more precisely, 32.5079 Mbps) TS signal of a broadcast program signal is converted into a 44.5 Mbps TS signal after being compressed by the MPEG standard for transmission in the FPU device on the transmission side. When a rate conversion unit for conversion is provided and used for transmission from a relay site to a wireless relay device, such a transmission rate conversion is not performed. This is a corresponding configuration.

  Incidentally, as in the technique described in Patent Document 1, it is necessary to synchronize the processing on the transmission side and the processing on the reception side. For this purpose, a clock is normally transmitted from the transmission side to the reception side. On the receiving side, the received signal is processed based on this clock. On the transmission side, when the transmission rate is converted, the input 32.5 Mbps transmission broadcast program signal TS signal is converted to a 44.7 Mbps TS signal. It is necessary to frequency-convert the synchronized clock.

On the other hand, the DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface) standard is known as one standard for transmitting MPEG standard TS signals. This is to transmit the above-mentioned MPEG standard 32.5 Mbps TS signal on a 270 Mbps asynchronous clock. In the case of an STL that transmits a TS signal (hereinafter referred to as a DVB-ASI signal) from the studio to a transmitting station (wireless repeater) in accordance with the DVB-ASI standard, the TS signal clock frequency (= 32.5079) MHz) and a frame synchronization signal F _sync indicating the start timing of each frame of the TS signal are transmitted.
JP 2006-33236 A

  By the way, when a DVB-ASI signal is sent from the studio to the transmitting station by STL, this DVB-ASI signal is sent as a radio wave signal in the microwave band, as described with reference to FIGS. For this reason, the transmitting station receives radio waves traveling straight from the studio. However, due to the roundness of the earth, the limit for receiving radio waves traveling straight is about 100 km. When an STL is configured with a remote island that is more than 100 km away from the mainland, DVB-ASI signals cannot be transmitted in the microwave band. In order to make this possible, it is conceivable to optically transmit a DVB-ASI signal using a submarine optical fiber.

However, many optical fiber devices usually transmit only TS signals, and do not support transmission of a frame signal F _sync indicating the start of a clock or TS signal frame. Therefore, it is conceivable that the transmitting station side regenerates the clock from the received TS signal and uses this to generate the frame signal F _sync .

  However, since the DVB-ASI signal is asynchronous, a sampling error or the like accumulates when the DVB-ASI signal is processed at the transmitting station on the receiving side. In some cases, when a clock is recovered from such a DVB-ASI signal using a PLL (Phase Locked Loop) circuit, the control voltage to the VCO (Voltage Controlled Oscilator) is temporarily increased. Swing and large jitter (phase fluctuation) occur in the recovered clock, which greatly affects the subsequent processing apparatus.

  An object of the present invention is to solve such a problem and to reproduce a clock in which phase fluctuation due to jitter or the like is suppressed from a received DVB-ASI signal and to remove fluctuations in the period of this DVB-ASI signal. It is to provide a signal reproducing apparatus.

In order to achieve the above object, the present invention provides a signal reproducing apparatus for reproducing a regular clock of a TS signal using a PLL circuit from a TS signal including a TS packet starting with a 47h (hexadecimal number) code. A 47h code detector that detects the 47h code for each TS packet of the TS signal and outputs a 47h code pulse at the timing of the 47h code, and divides the 47h code pulse by n (n is an integer of 2 or more). ), A phase difference detection circuit for detecting a phase difference Δφ between the phase reference clock from the frequency divider of the PLL circuit and the frequency division output pulse from the frequency divider, and the phase difference detection circuit The detected phase difference Δφ is divided into n phase differences, and when the 47h code pulse is ahead of the phase reference clock and when the 47h code pulse is behind the phase reference clock N divided phase differences having a total size of Δφ are generated and stored, and the phase difference dividing / storing circuit that stores and holds the divided phase difference generated by the phase difference dividing / storing circuit. based on, when the 47h code pulse is advanced in phase than the phase reference clock for each said phase reference clock, generates a phase alternate pulses advanced phase by the split retardation than the phase reference clock , the 47h when the code pulse is phase delayed from the phase reference clock for each said phase reference clock, phase alternate process for generating a phase alternate pulses the split retardation by the phase is delayed than the phase reference clock provided a circuit, is characterized in supplying the generated the phase alternate pulses and the phase reference clock said phase alternate processing circuit to a phase comparator for constituting the PLL circuit

  The present invention also provides a signal reproduction apparatus for reproducing a regular clock of a TS signal from a TS signal including a TS packet starting with a 47h (hexadecimal number) code by using a PLL circuit, and for each TS packet of the TS signal. 47h code detector that detects 47h code and outputs 47h code pulse at 47h code timing, a frequency divider that divides the 47h code pulse by n (n is an integer of 2 or more), and frequency division of the PLL circuit A phase difference detection circuit for detecting the phase difference Δφ between the phase reference clock from the detector and the divided output pulse from the frequency divider, and the phase difference Δφ detected by the phase difference detection circuit are divided into n to obtain a 47h code pulse Generate n divided phase differences of Δφ / n when the phase is ahead of the phase reference clock and when the 47h code pulse is behind the phase reference clock Based on the phase difference division / storage circuit to be stored and the divided phase difference generated by the phase difference division / storage circuit, when the phase of the 47h code pulse is ahead of the phase reference clock, Generates a phase substitution pulse whose phase is advanced by Δφ / n, and when the 47h code pulse is behind the phase reference clock, generates a phase substitution pulse whose phase is delayed by Δφ / n from the phase reference clock. And a phase replacement pulse generated by the phase replacement processing circuit and a phase reference clock are supplied to a phase comparator constituting the PLL circuit.

  According to the present invention, even when only the TS signal is transmitted, it is possible to reproduce a stable clock or frame signal in which the influence of the phase variation of the TS signal, such as jitter, is reduced. When reading from a memory in which TS signals are written and read out based on this clock in accordance with phase fluctuations, the write address in this memory overtakes the read address or the read address Can be prevented from overtaking the write address, and normal data can be output.

First, the basic configuration of the signal reproducing apparatus according to the present invention will be described with reference to FIG.
In FIG. 6, 1 is an S / P (serial / parallel) converter, 2 is an FPGA (Field Programmable Gate Array), 3 is a memory, 4 is a 47h code detector, 5 is a phase comparator, and 6 is an LPF (LPF). Low-pass filter), 7 is a VCO (voltage controlled oscillator), 8 is a frequency divider, 9 is an ASI modulator, 10 is a frame detector, 11 and 12 are frequency dividers, and 13 is a 270 MHz oscillator.

  In FIG. 12, for example, a serial DVB-ASI signal A output from the receiving-side FPU device 206 shown in FIG. 12 is supplied to the S / P converter 1 and converted into a parallel DVB-ASI signal to be stored in the memory 3. To be supplied. In this case, in FIG. 12, transmission between the FPU-TX 200 and the FPU-RX device 206 is performed via an optical fiber, for example, but is not limited thereto.

  Here, the TS signal of the serial DVB-ASI signal A has a clock frequency of 32.5079 MHz (clock cycle = 1 / 32.5079 μsec) and, as shown in FIG. 7, 204 bytes (= 1632 bits) from the TS packet array. It will be. This TS packet is composed of an 8-byte header, 196-byte data and parity, and the header is prefixed with a 47h code representing 1-byte hexadecimal number “47”. It is composed of a 3-byte PID (Packet IDentifier: packet ID) for identifying valid / invalid (NULL packet).

  The serial DVB-ASI signal A is obtained by modulating the 270 MHz clock shown in FIG. 8B with the serial TS signal having the clock frequency of 32.5079 MHz shown in FIG. 8A.

  The S / P converter 1 (FIG. 6) converts the serial DVB-ASI signal A having a clock frequency of 270 MHz into 8 bits (32.5079 MHz clock) for every 10 bits (clock) as shown in FIG. 8 (c). To a parallel signal of the number of bits of a 270 MHz clock in a period corresponding to one bit of a frequency TS packet. Therefore, the clock frequency of the obtained parallel DVB-ASI signal is 27 MHz as shown in FIG.

  FIG. 9 is a timing chart showing signals of the respective parts in FIG. 6, and the operation of the respective parts in FIG. 6 will be described below with reference to FIG.

  The S / P converter 1 converts the serial DVB-ASI signal A (FIG. 9A) having a clock frequency of 270 MHz into parallel for each TS packet as described in FIG. 8, and has a clock frequency of 27 MHz. The parallel DVB-ASI signal B (FIG. 9 (b)) is converted and output, and the 27 MHz clock (27M clock C: FIG. 9 (c)) is also output. As shown in FIG. 7, the serial TS packet is composed of 1632 bits, and the period is approximately 50 μsec (= 1632 bits / 32.5079 Mbps), and this is 204 pieces of 8-bit parallel data (= 1632 bits / 8). The parallel TS packet period is approximately 7.5 μsec (= 204/27 MHz). Accordingly, a serial TS packet of approximately 50 μsec is converted into a parallel TS packet of 7.5 μsec.

  Therefore, when one serial TS packet is converted into a parallel TS packet, the serial / parallel conversion process is suspended until the next serial TS packet starts. When the next serial TS packet starts, the serial / parallel conversion of this serial TS packet starts. Parallel conversion processing is performed. The obtained parallel DVB-ASI signal B (FIG. 9B) is an intermittent signal composed of 7.5 μsec parallel TS packets every approximately 50 μsec.

  Thus, in the S / P converter 1, serial / parallel conversion processing of the serial DVB-ASI signal A is performed, but the period of the intermittent parallel TS packet in the obtained parallel DVB-ASI signal B is obtained. A 7.5 μsec EN (ENable) signal D (FIG. 9D) representing (the above 7.5 μsec period: valid period) is also generated and output.

  A parallel DVB-ASI signal B having a clock frequency of 27 MHz (FIG. 9B) and a 27 MHz clock (27M clock) C obtained by dividing the clock frequency 270 MHz of the serial DVB-ASI signal A by 10 (FIG. 9C) The EN signal D (FIG. 9D) is supplied to the memory 3 formed in the FPGA 2.

  Here, the FPGA 2 includes a frequency divider 8, a frame detector 10, and two frequency dividers 11 and 12 together with the memory 3, but these are limited to those configured by the FPGA 2. However, these functions may be provided by a DSP (Digital Signal Processor), or a dedicated IC may be used as these, and there is no particular limitation.

  The phase comparator 5, LPF 6, VCO 7, and frequency divider 8 constitute a PLL circuit for generating a frequency division reference clock F 2 from the 47 h code of the parallel DVB-ASI signal B, and the 47 h code detector 4 Is provided.

  The parallel DVB-ASI signal B, 27M clock C, and EN signal D from the S / P converter 1 are supplied to the memory 3, and are determined by the EN signal D in the parallel TS signal B using the 27M clock C as a write clock. The signal of the valid period part, that is, the parallel TS packet is sequentially written. The parallel DVB-ASI signal B, the 27M clock C, and the EN signal D are supplied to the 47h code detector 4, and the 47h code indicating the head of the serial TS packet of the parallel DVB-ASI signal B is detected. The 47h code pulse E (FIG. 9E) is output. The 47h code detector 4 uses the 27M clock C and the EN signal D to detect a 47h code of hexadecimal “47” for each parallel TS signal B, and generates and outputs a 47h code pulse E. The 47h code pulse E is a pulse of 16.32 periods at 32.5079 MHz, that is, a pulse of approximately 19.9 kHz.

  The 47h code pulse E is supplied to the phase comparator 5. The phase comparator 5 forms a PLL circuit together with the LPF 6, the VCO 7 and the frequency divider 8, and the VCO 7 generates a reference clock F of 32.5079 MHz. This reference clock F is frequency-divided by 1632 by the frequency divider 8 to generate a phase reference clock F1 of approximately 19.9 kHz, which is supplied to the phase comparator 5 and phase-compared with the 47h code pulse E from the 47h code detector 4. The The phase error signal is smoothed by the LPF 6 and supplied to the VCO 7 as a control voltage. The VCO 7 is controlled by this control voltage, whereby the phase and frequency of the reference clock F output from the VCO 7 are synchronized with the 47h code pulse E.

  The frequency divider 8 also obtains an 8.127 MHz divided reference clock F2 obtained by dividing the 32.5079 MHz reference clock F from the VCO 7 by four.

The frequency division reference clock F2 from the frequency divider 8 is divided by 2 by the frequency divider 11, and the parallel TS packets described above are sequentially continued from the memory 3 using the obtained 4.0635 MHz clock as a read clock. And read. According to this, since one parallel TS packet is composed of 204 pieces of 8-bit parallel data, one parallel TS packet reading period is:
204 × 8 / 32.5079 μsec = 1632 / 32.5079 μsec = about 50 μsec
And equal to the period length of a serial TS packet with a clock frequency of 32.5079 MHz. As a result, 8-bit parallel data (32M data) G having a clock frequency of 32.5079 / 8 MHz, in which parallel TS packets are sequentially continued, is read from the memory 3. The 32M data G is supplied to the ASI modulator 9, and a parallel DVB-ASI signal H (FIG. 9 (g)) is generated using the 270 MHz clock from the 270 MHz oscillator 13, and transmitted to the next transmitting station. .

The 32M data G read from the memory 3 is supplied to the frame detector 10 and is divided by 8 obtained by further dividing the divided reference clock F2 from the divider 8 by 2 by the 2 divider 12. An F _sync signal I indicating the head of the frame is generated using the clock. This F _sync signal I is also transmitted to the next transmitting station together with the parallel DVB-ASI signal H from the ASI modulator 9.

Furthermore, the frequency division reference clock F2 from the frequency divider 8 is transmitted to the next transmitting station together with the parallel DVB-ASI signal H from the ASI modulator 9 and the F _sync signal I from the frame detector 10.

  FIG. 10 is a timing chart showing the operation of the PLL circuit in FIG.

FIG. 10A shows the phase error output from the phase comparator 5 when the phase of the phase reference clock F1 is the reference phase θ _{S and} the phase shift (phase difference) of the 47h code pulse E with respect to the reference phase θ _S is small. When the phase of the 47h code pulse E coincides with the reference phase θ _S as shown in FIGS. 10A and 10A, the phase error voltage from the phase comparator 5 is shown. Δθ is zero. In this case, the VCO 7 is controlled to keep the current phase and frequency of the reference clock F as they are. Further, as shown in FIGS. 10A and 10B, when the phase of the 47h code pulse E advances smaller than the reference phase θ _S , the positive phase error voltage Δθ corresponding to the phase difference is As a result, the VCO 7 is controlled so as to increase the frequency of the reference clock F so that the reference phase θ _S of the phase reference clock F1 advances small (a short left arrow). Further, as shown in FIGS. 10A and 10C, when the phase of the 47h code pulse E is delayed by a smaller amount than the reference phase θ _S , the negative phase error voltage Δθ corresponding to the phase difference is As a result, the VCO 7 is controlled so as to decrease the frequency of the reference clock F so that the reference phase θ _S of the phase reference clock F1 is slightly delayed (short arrow pointing to the right). Thus, when the phase difference between the phase of the 47h code pulse E and the reference phase θ _S is small, the PLL circuit operates so that the 47h code pulse E and the phase reference clock F1 are phase-synchronized with a small control voltage. Will be controlled.

FIG. 10B shows the phase error voltage Δθ output from the phase comparator 5 when the phase difference of the 47h code pulse E with respect to the phase of the phase reference clock F1, ie, the reference phase θ _S is large. As shown in FIGS. 10B and 10A, when the phase of the 47h code pulse E advances more than the reference phase θ _S, a large positive phase error voltage Δθ corresponding to the phase difference becomes the phase comparator 5. As a result, the VCO 7 is controlled so as to increase the frequency of the reference clock F so that the reference phase θ _S of the phase reference clock F 1 advances greatly (long left arrow). Further, as shown in FIGS. 10B and 10B, when the phase of the 47h code pulse E is greatly delayed from the reference phase θ _S, a large negative phase error voltage Δθ corresponding to the phase difference is generated. As a result, the VCO 7 is controlled so that the frequency of the reference clock F is lowered and the reference phase θ _S of the phase reference clock F1 is greatly delayed (long arrow pointing to the right). As described above, even when the phase difference between the phase of the 47h code pulse E and the reference phase θ _S is large, the control voltage is increased in this case, but the 47h code pulse E and the phase reference clock F1 are phase-synchronized. , The PLL circuit is controlled.

  Thus, if the phase of the 47h code pulse changes drastically due to jitter or the like, the control voltage of the VCO 7 changes accordingly and the 47h code pulse E and the phase reference clock F1 are synchronized in phase. The control voltage of the VCO 7 changes drastically, the frequency of the reference clock F output from the VCO 7 changes suddenly, and the frequency and phase of the phase reference clock F1 and the divided reference clock F2 obtained by frequency division change suddenly. . That is, if the phase of the 47h code changes suddenly due to jitter or the like, the phase reference clock F1 and the frequency division reference clock F2 are greatly affected.

  On the other hand, the present applicant has proposed an invention in which the PLL circuit is controlled by removing the phase fluctuation such as jitter that greatly changes the phase of the 47h code pulse (Japanese Patent Application No. 2007-). 209089).

  In the present invention, a predetermined phase range is set as an appropriate phase range centering on the phase of the phase reference clock F1 with respect to the phase reference clock F1, and the phase difference of the 47h code pulse E with respect to the phase reference clock F1 is When the phase is within the proper phase range, the 47h code pulse E and the phase reference clock F1 are supplied to the phase comparator 5 of the PLL circuit, but the phase difference of the 47h code pulse E from the phase reference clock F1 due to jitter or the like. Is larger than this proper phase range, instead of the 47h code pulse E, an alternative pulse delayed by one clock cycle of the reference clock F with respect to the phase reference clock F1 is supplied to the phase comparator 5 This eliminates large phase fluctuations that exceed this proper range of the 47h code pulse E. , So that the divided reference clock F2 that is not affected like jitter can be obtained.

  By the way, in the present invention by the present applicant, the read clock of the memory 3 output from the frequency divider 11 is one in which the influence of the large phase fluctuation of the 47h code pulse E is removed. C is affected by the phase fluctuation, and the write address in the memory 3 advances or delays with respect to the read address. Therefore, when the jitter distribution is asymmetric in time, the write address may overtake the read address or may be overtaken by the read address, and there may be a situation in which data reading from the memory 3 becomes abnormal. Will occur.

  The present invention solves this problem and makes it possible to generate a divided reference clock F2 that is not affected by a large phase fluctuation of the 47h code pulse E due to jitter or the like. A form is demonstrated using drawing.

  FIG. 1 is a block diagram showing an embodiment of a signal reproducing apparatus according to the present invention, wherein 14 is a frequency divider, 15 is a phase difference detection circuit, 16 is a phase difference division / storage circuit, and 17 is a phase substitution processing circuit. Therefore, parts corresponding to those in FIG.

  In the figure, the 47h code pulse E output from the 47h code detector 4 is supplied to the frequency divider 14 and the frequency thereof is divided by 1 / n (where n is an integer of 2 or more). A frequency-divided pulse J whose phase is synchronized with the 47h code pulse E is obtained at a period n times the period of the pulse E (thus, a period n times the period of the TS packet shown in FIG. 7). This frequency-divided pulse J is supplied to the phase difference detection circuit 15, the phase reference clock F 1 from the frequency divider 8 and the phase difference K are detected every n cycles, and supplied to the phase difference division / storage circuit 16. The phase difference dividing / storing circuit 16 divides the supplied phase difference K, holds the phase difference (divided phase difference) L obtained by the division, and sequentially performs the phase at the timing of the phase reference clock F1. This is supplied to the alternative processing circuit 17. Based on this divided phase difference L, the phase substitution processing circuit 17 generates a phase substitution pulse M from the phase reference clock F1, and supplies it to the phase comparator 5 together with the phase reference clock F1. The phase comparator 5 compares the phase substitution pulse M from the phase substitution processing circuit 17 with the phase reference clock F1, detects the phase error voltage Δθ, supplies it to the VCO 7 via the LPF 6, and supplies this to the VCO 7. Controls the oscillation frequency.

  In the phase difference division / storage circuit 16, the stored divided phase difference L is always supplied to the phase substitution processing circuit 17, and when a new phase difference K is supplied from the phase difference detection circuit 15, it is stored so far. The divided phase difference L is updated to a new divided phase difference L obtained from the newly supplied phase difference K, and the new divided phase difference L is supplied to the phase substitution processing circuit 17.

  Further, the phase difference K detected by the phase difference detection circuit 15 depends on the phase relationship between the advance and delay between the frequency division pulse J from the frequency divider 14 and the phase reference clock F1 from the frequency divider 8. It consists of positive and negative sign information indicating the advance and delay and size information indicating the size. Similarly, the divided phase difference L generated by the phase difference dividing / storing circuit 16 includes code information L1 and size information L2.

The phase difference division / storage circuit 16 divides the phase difference Δφ represented by the magnitude information of the phase difference K from the phase difference detection circuit 15 into n pieces. Now, assuming that the phase of the 47h code pulse E is advanced by Δφ with respect to the phase reference clock F1, the code information L1 of the divided phase difference L at that time is set to L1 (+). Assuming that the magnitude information L2 of the divided phase difference L is L2 (+),
Δφ / n, Δφ / n, ..., Δφ / n, Δφ / n
As described above, n pieces of size information L2 (+) having a size of Δφ / n are created and stored. Similarly, when the 47h code pulse E is delayed by the phase Δφ from the phase reference clock F1 and the code information L1 is L1 (−), n pieces of magnitude information L2 (−) of Δφ / n are similarly generated. Remember each.

  The n pieces of magnitude information L2 (+) and L2 (−) for the code information L1 (+) and L1 (−) created in this way is the phase Δφ of the 47h code pulse E than the phase reference clock F1. When the sign information L1 is L1 (+) and the 47h code pulse E is output from the 47h detector 4, the magnitude information L2 (+) of Δφ / n is sequentially added together with the sign information L1 (+). The 47h code pulse E is also supplied to the phase substitution processing circuit 17 as the divided phase difference L, and the 47h code pulse E is delayed by the phase Δφ from the phase reference clock F1 and the code information L1 is L1 (−). Is output from the detector 4h, n pieces of magnitude information L2 (−) of Δφ / n are sequentially supplied to the phase substitution processing circuit 17 as the divided phase difference L together with the code information L1 (−). Is done.

  FIG. 2 is a block diagram showing a specific example of the phase substitution processing circuit 17 in FIG. 1, wherein 17a and 17b are delay means, and 17c and 17d are changeover switches.

  In the figure, the phase reference clock F1 from the frequency divider 8 (FIG. 1) is supplied to the delay means 17a and 17b, and to the + terminal of the changeover switch 17c and the-terminal of the changeover switch 17d. The output pulse of the delay means 17a is supplied to the negative terminal of the changeover switch 17c, and the output pulse of the delay means 17b is supplied to the positive terminal of the changeover switch 17d. The change-over switches 17c and 17d are switch-controlled by code information L1 of the phase difference L supplied from the phase difference dividing / storage circuit 16 at the timing of the phase reference clock F1.

  With the switching control of the changeover switch 17c, when the code information L1 in which the phase of the 47h code pulse E is advanced by Δφ with respect to the phase reference clock F1 is L1 (+), the changeover switch 17c is closed to the + terminal side, The phase reference clock F1 supplied from the frequency divider 8 is selected and supplied to the phase comparator 5 (FIG. 1) as the phase substitute pulse M. Further, when the code information L1 in which the 47h code pulse E is delayed in phase by Δφ with respect to the phase reference clock F1 is L1 (−), the changeover switch 17c is closed to the −terminal side and supplied from the frequency divider 8. The phase reference clock F1 delayed by the delay means 17a is selected and supplied to the phase comparator 5 (FIG. 1) as the phase substitute pulse M.

  Although not shown in FIG. 2, the phase substitution processing circuit 17 slightly delays the phase reference clock F1 so that the switching timing of the changeover switches 17c and 17d does not coincide with the timing of the phase reference clock F1.

  When the sign information L1 in which the phase of the 47h code pulse E is advanced by Δφ with respect to the phase reference clock F1 is L1 (+) by the changeover control of the changeover switch 17d, the changeover switch 17d is closed to the + terminal side, The phase reference clock F1 supplied from the frequency divider 8 and delayed by the delay means 17b is selected and supplied to the phase comparator 5 (FIG. 1) as the phase reference clock F1. On the other hand, when the code information L1 in which the 47h code pulse E is delayed in phase by Δφ with respect to the phase reference clock F1 is L1 (−), the changeover switch 17d is closed to the − terminal side and supplied from the frequency divider 8. The phase reference clock F1 is selected and supplied to the phase comparator 5 (FIG. 1) as the phase reference clock F1.

  Here, in the case of this specific example, when the phase difference K of Δφ is supplied from the phase difference detection circuit 15, the phase difference dividing / storing circuit 16 divides the phase difference by Δφ / n into n pieces of Δφ / n. The magnitude information L2 is created and stored, and every time the phase reference pulse F1 is supplied from the frequency divider 8, the magnitude information L2 of Δφ / n is combined with the code information L1 as the divided phase difference L and the delay means 17a. , 17b. Thus, the phase reference pulse F1 supplied from the frequency divider 8 is delayed by Δφ / n by the delay means 17a and the delay means 17b and supplied to the changeover switches 17c and 17d, respectively.

  Therefore, with respect to the phase reference pulse F1 from the delay means 17b supplied to the + terminal of the changeover switch 17d, the phase reference pulse supplied as a phase substitute pulse M from the frequency divider 8 to the + terminal of the changeover switch 17c. F1 has a phase advanced by Δφ / n, and the phase reference pulse F1 supplied from the frequency divider 8 to the negative terminal of the changeover switch 17d is applied to the negative terminal of the changeover switch 17c from the delay means 17a. As the phase substitute pulse M, the phase reference pulse F1 supplied is delayed in phase by Δφ / n.

  Therefore, when the 47h code pulse E is advanced in phase by Δφ with respect to the phase reference clock F1 and the code information L1 is L1 (+), the changeover switches 17c and 17d are closed to the + terminal side. With respect to the phase reference pulse F1 supplied from 17d to the phase comparator 5, the phase substitute pulse M supplied from the changeover switch 17c to the phase comparator 5 is advanced in phase by Δφ / n. The next phase reference pulse supplied from the frequency divider 8 has a phase advanced by Δφ / n.

  When the 47h code pulse E is delayed in phase by Δφ with respect to the phase reference clock F1 and the sign information L1 is L1 (−), the selector switches 17c and 17d are closed to the − terminal side, and therefore the phase comparison is performed from the selector switch 17d. The phase substitution pulse M supplied from the changeover switch 17c to the phase comparator 5 is delayed in phase by Δφ / n with respect to the phase reference pulse F1 supplied to the frequency divider 5, so that the frequency divider 8 The next phase reference pulse to be supplied is delayed in phase by Δφ / n.

  Thus, in this specific example, when the phase of the 47h code pulse E is advanced by Δφ with respect to the phase reference clock F1, the phase of the phase comparator 5 is advanced by Δφ / n with respect to the phase reference pulse F1. When the phase alternative pulse M is supplied and the phase of the 47h code pulse E is delayed by Δφ with respect to the phase reference clock F1, the phase is set to the phase comparator 5 by Δφ / n with respect to the phase reference pulse F1. The delayed phase substitution pulse M is supplied. As a result, the phase reference pulse F1 from the frequency divider 8 gradually approaches the phase of the 47h code pulse E.

FIG. 3A is a block diagram showing a specific example of the delay means 17a and 17b in FIG. 2, and 18 ₁ to 18 _m (where m is an integer of m <n) is a DFF (D-type flip-flop). And 19 is a selector. FIG. 3B is a timing chart showing the operation of this specific example.

In the specific example shown in FIG. 3A, m DFFs 18 ₁ to 18 _m are connected in series, and _{one of the} output pulses Q _{1 to} Q _m output from the Q terminals of these DFFs 18 ₁ to 18 _m is selected by the selector 19. Is configured to select.

For example, a reference clock F output from the VCO 7 in FIG. 1 is supplied to each of the DFFs 18 ₁ to 18 _m as a clock CK input to the CK terminal, and is input from the D terminal at the rising timing of the reference clock F. Data D is captured, and the level (“H” (high level), “L” (low level)) of the output pulse Q output from the Q terminal is set to the level of the captured data D.

The input data D of the _first stage DFF 18 ₁ is the phase reference clock F 1 from the frequency divider 8 (FIG. 1), and the data D input to the second stage DFF 18 ₂ is the output pulse from the Q terminal of the first stage DFF 18 _1. Q ₁ and data D input to the third-stage DFF 18 ₃ is an output pulse Q ₂ from the Q terminal of the second-stage DFF 18 ₂ . Thus, in the second and subsequent stages of DFF 18 _i (where i = 2, 3,..., M), the output pulse Q _i-1 output from the preceding stage DFF 18 _i-1 is supplied as data D. The

  Next, the operation of this specific example will be described with reference to FIG.

When the period of the reference clock F as a clock CK and T _S, the pulse width (period) T _W phase reference clock F1 is shorter than the period T _S, which is approximately equal to the pulse width to the period T _S. Thus, one of the reference clock F will exist in a phase period of the reference clock F1 (level "H") in T _W. In other words, for each period of the phase reference clock F1, but always one of the reference clock F will be present within the period T _W of the phase reference clock F1.

Therefore, in FIG. 3 (b), when the phase reference clock F1 to the first stage DFF18 ₁ is supplied as the data D, the reference clock F as a clock CK supplied within the period T _W of the phase reference clock F1 (1) the rising edge level "H" period T _W of the phase reference clock F1 incorporated in, Q terminal of the DFF18 ₁ becomes level "H". Then, the next time the reference clock F (2) is supplied, since the elapsed time T _W phase reference clock F1, Q terminal of the DFF18 ₁ becomes level "L". Therefore, DFF18 from ₁ Q terminal, phase-synchronized with the rising edge of the reference clock F (1) to be supplied within the period T _W of the phase reference clock F1, substantially equal pulse width period T _S of the reference clock F A _TQ output pulse Q ₁ is output.

Output pulses to Q ₁ the DFF18 ₁ level from the Q terminal "H" is supplied to the DFF18 ₂ of the second stage as data D. In the DFF18 _2, and level "H" of the pulse Q ₁ is captured at the rising edge of this the supplied output pulses to Q ₁ reference clock F supplied immediately after the rising edge (2), the DFF18 ₂ of Q When the terminal becomes level “H” and the reference clock F (3) is supplied next, since the period T _Q of the pulse Q ₁ has passed, the Q terminal of the DFF 18 ₂ becomes level “L”. Thereby, the phase of the Q terminal of the DFF 18 ₂ is synchronized with the rising edge of the reference clock F (2) supplied during the period T _Q of the output pulse Q ₁ of the level “H” from the Q terminal of the DFF 18 ₁ . An output pulse Q ₂ having a pulse width T _Q substantially equal to the cycle T _S of the reference clock F is output. Accordingly, the output pulse Q ₂ from the Q terminal of the DFF 18 ₂ is delayed in phase by one cycle T _S of the reference clock F from the output pulse Q ₁ from the Q terminal of the DFF 18 ₁ .

Similarly, in the DFF 18 ₃ to which the output pulse Q ₂ from the Q terminal of the DFF 18 ₂ is supplied as data D, the phase is delayed from the Q terminal by one cycle T _S of the reference clock F from the pulse Q ₂ . The pulse Q ₃ is output, and one cycle T _S of the reference clock F sequentially from each of the DFFs 18 ₁ , 18 ₂ , 18 ₃ ,..., 18 _m in one cycle of the phase reference clock F 1. Thus, m pulses Q ₁ , Q ₂ , Q ₃ ,..., Q _m whose phases are sequentially delayed are obtained. That is, the output pulses to Q ₁ from DFF18 ₁ is a pulse phase reference clock F1 in phase, the output pulse Q ₂ from DFF18 ₂ was only phase delayed by one period T _S of the reference clock F from the phase reference clock F1 a pulse, DFF18 output pulse Q ₃ from ₃ is only twice pulses whose phase is delayed in period T _S of the reference clock F from the phase reference clock F1, ......, the output pulse Q _m from DFF18 _m This is a pulse whose phase is delayed by m times the period T _S of the reference clock F with respect to the phase reference clock F1.

The output pulses Q ₁ , Q ₂ , Q ₃ ,..., Q _m from these DFFs 18 ₁ , 18 ₂ , 18 ₃ ,..., 18 _m are supplied to the selector 19, and the phase difference dividing / storing circuit 16 ( A pulse Q _j (where j = 1, 2, 3,..., M) corresponding to the magnitude information L2 at that time from FIG. 1) is selected. Here, the corresponding pulse Q _j is a pulse delayed in phase by Δφ / n phase of the magnitude information L2 from the phase reference clock F1.

  The pulse selected by the selector 19 is supplied to the negative terminal of the changeover switch 17c in FIG. 2 (in the case of the delay means 17a) or the positive terminal of the changeover switch 17d (in the case of the delay means 17b).

  In this way, the delay means 17a and 17b in FIG. 2 can obtain a pulse whose phase is delayed by the divided phase difference Δφ / n of the magnitude information L2 set at this time from the phase reference clock F1. Become.

  FIG. 4A is a block diagram showing another specific example of the delay means 17a and 17b in FIG. 2, wherein 20 is a register, 21 is a coincidence detector, 22 is a multiplier, 23 is a counter, and 24 is an AND. It is a gate. FIG. 4B is a timing chart showing the operation of this specific example.

  The specific example shown in FIG. 4A includes a register 20, a coincidence detector 21, a multiplier 22, a counter 23, and an AND gate 24.

  Each time the magnitude information L2 of the division phase difference L is supplied from the phase difference division / storage circuit 16 (FIG. 1), the magnitude information L2 is accumulated in the register 20. The accumulated size information L2 is supplied to the coincidence detector 21.

On the other hand, the phase reference clock F1 of level “H” is supplied to the counter 23 as a clear pulse CL, and is also inverted in level and supplied to the AND gate 24. The AND gate 24, the reference clock F also supplied, as shown in FIG. 4 (b), with the exception of the period T _W of the phase reference clock F1 which is level inversion, is supplied as a clock CK to the counter 23 The

In this specific example, similarly to the specific example shown in FIG. 3, if the period of the reference clock F as the clock CK is T _S , the pulse width (period) T _W of the phase reference clock F1 is equal to the period T _The pulse width is shorter than _S but substantially equal to the period T _S. Thus, one of the reference clock F will exist in a phase period of the reference clock F1 (level "H") in T _W. In other words, for each period of the phase reference clock F1, but always one of the reference clock F will be present within the period T _W of the phase reference clock F1.

  The counter 23 is cleared at the timing of the rising edge (front edge) of the phase reference clock F1 of level “H”, and when the reference clock F is supplied via the AND gate 24, the reference clock F is supplied. Every time the value is incremented from 1 to 1. Accordingly, the count value N of the counter 23 is cleared to a value of 0 each time the phase reference clock F1 is supplied, and represents the number of inputs of the reference clock F after the phase reference clock F1 is supplied. Is.

The count value N of the counter 23 is supplied to the multiplier 22, and the count value N is converted into a time length TD. Here, assuming that the period of the phase reference clock F1 is T _F1 , the phase reference clock F1 is obtained by dividing the reference clock F by 1632. Therefore, the period T _S of the reference clock F (reference clock F with respect to the phase reference clock F1) The phase difference for one of
T _S = T _F1 / 1632
It becomes. Therefore, the time T _D required from the counter 23 being cleared by the phase reference clock F1 until the count value N becomes N is
T _D = N · T _F1 / 1632
As shown in FIG. 4B, it increases with the count of the counter 23. The time T _D is supplied to the coincidence detector 21. The coincidence detector 21 compares the time TD with the magnitude information L2 from the register 20, and when the two coincide, or when they coincide within a predetermined error value range, FIG. As shown, a coincidence pulse P is output. The coincidence pulse P is a phase delay pulse of magnitude information L2 of the divided phase difference L from the phase reference clock F1, and is supplied to the negative terminal of the changeover switch 17c as an output of the delay means 17a in FIG. 2 is supplied to the + terminal of the changeover switch 17d as the output of the delay means 17b.

  In this manner, the coincidence detector 21 obtains a phase-lag pulse of the magnitude information L2 of the divided phase difference L from the phase reference clock F1.

  FIG. 5 is a timing chart showing the operation of the PLL circuit shown in FIG. 1. Signals corresponding to those in FIG.

  FIG. 5A shows a state in which the 47h code pulse E is in phase synchronization with the phase reference clock F1 and the phase reference clock F1 (normal phase state), and the 47h code E from the 47h code detector 4 is When the phase is synchronized with the phase reference clock F1, the magnitude information of the phase difference signal K output from the phase difference detection circuit 15 is Δφ = 0, and the sign information is positive or negative ( When the magnitude information is Δφ = 0, the sign information is determined to be either positive or negative, but in the following, the sign information is assumed to be positive). Accordingly, the divided phase difference L stored in the phase difference dividing / storing circuit 16 and supplied to the phase substitution processing circuit 17 has the code information L1 of L1 (+) and the magnitude information L2 of 0.

  Therefore, in the phase substitution processing circuit 17, the magnitude information L2 (+) of Δφ / n = 0 in FIG. 2 is supplied to the delay means 17a and 17b, respectively, and the delay amount 0 is set for each. Therefore, the phase reference pulse F1 supplied from the frequency divider 8 to the delay means 17a and 17b is output without being delayed. The output pulse of the delay means 17a is supplied to the-terminal of the changeover switch 17c, and the output pulse of the delay means 17b is supplied to the + terminal of the changeover switch 17d. The phase reference pulse F1 from the frequency divider 8 is supplied to the + terminal of the changeover switch 17c and the-terminal of the changeover switch 17d. At this time, since the sign information L1 of L1 (+) is supplied to the changeover switches 17c and 17d, the changeover switches 17c and 17d are closed to the + terminal side. Therefore, in the changeover switch 17c, the phase reference pulse F1 from the frequency divider 8 is selected as the phase substitute pulse M, and in the changeover switch 17d, the output pulse of the delay means 17b is selected as the phase reference pulse F1, respectively. It is supplied to the phase comparator 5 (FIG. 1). At this time, the delay amount of the delay means 17b is set to 0, and the phase reference clock F1 supplied to the delay means 17b is output without being delayed. Therefore, the phase substitute pulse M supplied from the changeover switch 17c to the phase comparator 5 The phase reference clock F1 supplied from the changeover switch 17c to the phase comparator 5 is in phase.

  In this way, in the normal phase state, as shown in FIG. 5A, the phase substitution pulse M is in phase with the 47h code pulse E, and the phase supplied from the phase comparator 5 to the LPF 6 The error signal Δθ is zero.

  FIG. 5B shows a state in which the phase of the 47h code pulse E is advanced by Δφ from the phase reference clock F1 (a state in which the phase has advanced), and the phase difference output from the phase difference detection circuit 15 is shown. The magnitude information of the signal K is Δφ, and the sign information is positive. Therefore, the divided phase difference L stored in the phase difference dividing / storing circuit 16 and supplied to the phase substitution processing circuit 17 is that the code information L1 is L1 (+) and the magnitude information L2 (+) is Δφ / n.

  In the phase substitution processing circuit 17 shown in FIG. 2, when the code information L1 is L1 (+), the phase is delayed by Δφ / n by the delay means 17b to which the magnitude information L2 (+) of Δφ / n is supplied. The phase reference clock F1 is selected by the changeover switch 17d as the phase reference clock F1 and supplied to the phase comparator 5 (FIG. 1). At the same time, the phase reference clock F1 from the frequency divider 8 is selected by the changeover switch 17c and supplied to the phase comparator 5 (FIG. 1) as the phase substitute pulse M.

  As a result, the phase substitute pulse M whose phase is compared with the phase reference clock F1 by the phase comparator 5 is always a pulse whose phase is advanced by Δφ / n from the phase reference clock F1.

  Although FIG. 5B shows the first phase alternative pulse M, the phase reference clock F1 for phase comparison by the phase comparator 5 also for the subsequent (n−1) phase alternative pulses M. Is a phase difference Δφ / n.

  In this way, in the state in which the phase of the 47h code pulse E is advanced, the phase substitution pulse M is advanced in phase by Δφ / n from the phase reference clock F1, and the phase difference is sufficiently larger than the phase difference Δφ. The reduced phase substitution pulse M is supplied to the phase comparator 5. The phase error signal Δθ supplied from the phase comparator 5 to the LPF 6 corresponds to this phase difference, and is output from the VCO 7 as compared with the case where the 47h code pulse E is supplied directly to the phase comparator 5 (FIG. 6). The frequency fluctuation of the reference clock F is small. Therefore, the influence of large and abrupt jitter on the 47h code pulse E of the reference clock F is greatly reduced.

  FIG. 5C shows a state in which the phase of the 47h code pulse E is delayed by Δφ from the phase reference clock F1 (a state in which the phase is delayed). The phase difference output from the phase difference detection circuit 15 is shown in FIG. The magnitude information of the signal K is Δφ, and the sign information is negative. Therefore, the divided phase difference L stored in the phase difference dividing / storing circuit 16 and supplied to the phase substitution processing circuit 17 is that the code information L1 is L1 (−) and the magnitude information L2 (−) is Δφ / n.

  In the phase substitution processing circuit 17 shown in FIG. 2, when the code information L1 is L1 (−), the phase is delayed by Δφ / n by the delay means 17a to which the magnitude information L2 (−) of Δφ / n is supplied. The phase reference clock F1 is selected as the phase substitute pulse M by the changeover switch 17c and supplied to the phase comparator 5 (FIG. 1). At the same time, the phase reference clock F1 from the frequency divider 8 is selected by the changeover switch 17d and supplied to the phase comparator 5 (FIG. 1).

  Thereby, the phase substitute pulse M whose phase is compared with the phase reference clock F1 by the phase comparator 5 is always a pulse whose phase is delayed by Δφ / n from the phase reference clock F1.

  In FIG. 5C, the first phase alternative pulse M is shown, but the phase reference clock F1 in which the phase comparator 5 also performs phase comparison for the subsequent (n−1) phase alternative pulses M. Is a phase difference Δφ / n.

  In this way, in the state where the 47h code pulse E is delayed in phase from the phase reference clock F1, the phase substitute pulse M is phase-delayed by Δφ / n by the phase reference clock F1, and therefore, the phase substitute pulse M is more delayed than the phase reference clock F1. The phase substitute pulse M whose phase is delayed by Δφ / n and whose phase difference is sufficiently reduced with respect to the phase difference Δφ is supplied to the phase comparator 5. The phase error signal Δθ supplied from the phase comparator 5 to the LPF 6 corresponds to this phase difference, and is output from the VCO 7 as compared with the case where the 47h code pulse E is supplied directly to the phase comparator 5 (FIG. 6). The frequency fluctuation of the reference clock F is small. Therefore, the influence of the jitter that changes abruptly at the 47h code pulse E of the reference clock F is greatly reduced.

  In the above embodiment, the phase difference Δφ representing the magnitude information of the phase difference K detected by the phase difference detector 15 in FIG. 1 is equally divided into n in the phase difference division / storage circuit 16. Thus, n pieces of magnitude information L2 of Δφ / n of the divided phase difference L are generated, and these are sequentially supplied to the phase substitution processing circuit 17 until the next phase difference K is supplied, and the phase reference clock is supplied. For each F1, a phase alternative pulse M advanced by Δφ / n or delayed by Δφ / n, that is, advanced by the same phase or delayed, is generated, but the present invention is not limited to this. If the total phase difference in the period until the next phase difference K is supplied becomes the phase difference Δφ representing the magnitude information of the phase difference K detected by the phase difference detector 15, the next phase difference K is supplied. Sequential magnitude information L of the divided phase difference L within the period until The may be made different.

  For example, during the period until the next phase difference K is supplied, the magnitude information L2 of the divided phase difference L is first increased, the phase difference of the phase alternative pulse M with respect to the phase reference clock F1 is increased, As time elapses, the magnitude information L2 of the divided phase difference L is reduced to gradually reduce the phase difference of the phase substitute pulse M with respect to the phase reference clock F1, or within a period until the next phase difference K is supplied. The phase difference of the phase alternative pulse M with respect to the phase reference clock F1 is set to a large constant value during the first half period, and the phase difference of the phase alternative pulse M with respect to the phase reference clock F1 is set to a small constant value during the latter half period. The sequential magnitude information L2 of the divided phase difference L can be made different in the phase difference dividing / storage circuit 16, for example.

  As described above, even if the phase of the 47h code pulse E changes drastically due to jitter or the like, it is possible to generate the divided reference clock F2 that is not affected by this, and the jitter of the 47h code pulse E or the like. Even if the phase changes greatly, the operation is performed so that the divided reference clock F2 follows this over the n periods of the 47h code pulse E, so that the write address catches up with the read address in the memory 3 or the read address is changed. The situation of overtaking can be prevented.

An F _sync (frame synchronization) signal I indicating the head of the frame generated by the frame detector 10 from the 32M data G read from the memory 3 is divided into two by the frequency division reference clock F2 from the frequency divider 8. Since it is generated by using the divided by 8 clock obtained by further dividing the frequency by the frequency divider 12, this F _sync signal I can also be reproduced normally.

It is a block block diagram which shows one Embodiment of the signal reproducing | regenerating apparatus by this invention. It is a block block diagram which shows the other specific example of the phase substitution processing circuit in FIG. It is a block diagram which shows one specific example of the delay means in FIG. It is a block diagram which shows the other specific example of the delay means in FIG. FIG. 2 is a timing diagram showing an operation of the PLL circuit in FIG. 1. It is a block block diagram which shows the basic composition of the signal reproducing | regenerating apparatus by this invention. It is a figure which shows the format of the TS packet of a serial TS signal. FIG. 7 is a timing chart showing the operation of the S / P converter in FIG. 6. FIG. 7 is a timing chart showing signals at various parts in FIG. 6. It is a timing diagram which shows operation | movement of the conventional PLL circuit. It is a block block diagram which shows an example of the conventional TSL radio transmission system using a FPU apparatus. It is a block block diagram which shows the other example of the conventional radio transmission system of TSL using FPU apparatus.

Explanation of symbols

1 S / P converter 3 Memory 4 47h code detector 5 Phase comparator 6 LPF
7 VCO
8 Divider 9 ASI Modulator 10 Frame Detector 11, 12 2 Divider 13 270 MHz Oscillator 14 Divider 15 Phase Difference Detection Circuit 16 Phase Difference Division / Storage Circuit 17 Phase Substitution Processing Circuit 17a, 17b Delay Means 17c, 17d changeover switch 18 ₁ to 18 _m DFF
19 selector 20 register 21 coincidence detector 22 multiplier 23 counter 24 AND gate

Claims (2)

A signal reproduction device for reproducing a regular clock of the TS signal from a TS signal including a TS packet starting with a 47h (hexadecimal number) code using a PLL circuit,
A 47h code detector that detects the 47h code for each TS packet of the TS signal and outputs a 47h code pulse at the timing of the 47h code;
A frequency divider for dividing the 47h code pulse by n (n is an integer of 2 or more);
A phase difference detection circuit for detecting a phase difference Δφ between the phase reference clock from the frequency divider of the PLL circuit and the frequency-divided output pulse from the frequency divider;
The phase difference Δφ detected by the phase difference detection circuit is divided into n phase differences, and when the phase of the 47h code pulse is ahead of the phase reference clock and when the 47h code pulse is shifted from the phase reference clock A phase difference dividing / storing circuit that generates and stores n divided phase differences whose total magnitude is Δφ when the phase is delayed, and
Based on the phase difference the split retardation generated by the split-storage circuit, when the 47h code pulse is advanced in phase than the phase reference clock for each said phase reference clock, from the phase reference clock also produce the split retardation by the phase alternate pulses advanced phase, when the phase is delayed from the 47h code pulses the phase reference clock for each said phase reference clock, the division than the phase reference clock A phase substitution processing circuit for generating a phase substitution pulse whose phase is delayed by the phase difference;
A signal reproducing apparatus, characterized in that the phase substitution pulse generated by the phase substitution processing circuit and the phase reference clock are supplied to a phase comparator constituting the PLL circuit. A signal reproduction device for reproducing a regular clock of the TS signal from a TS signal including a TS packet starting with a 47h (hexadecimal number) code using a PLL circuit,
A 47h code detector that detects the 47h code for each TS packet of the TS signal and outputs a 47h code pulse at the timing of the 47h code;
A frequency divider for dividing the 47h code pulse by n (n is an integer of 2 or more);
A phase difference detection circuit for detecting a phase difference Δφ between the phase reference clock from the frequency divider of the PLL circuit and the frequency-divided output pulse from the frequency divider;
The phase difference Δφ detected by the phase difference detection circuit is divided into n, and when the phase of the 47h code pulse is ahead of the phase reference clock and when the phase of the 47h code pulse is delayed from the phase reference clock. A phase difference dividing / storing circuit that generates and stores n divided phase differences having a magnitude of Δφ / n when
Based on the divided phase difference generated by the phase difference dividing / storing circuit, when the phase of the 47h code pulse is ahead of the phase reference clock, the phase is shifted by Δφ / n from the phase reference clock. Phase substitution processing that generates a phase substitution pulse that is advanced and generates a phase substitution pulse that is delayed in phase by Δφ / n from the phase reference clock when the 47h code pulse is behind the phase reference clock. Circuit and
A signal reproducing apparatus, characterized in that the phase substitution pulse generated by the phase substitution processing circuit and the phase reference clock are supplied to a phase comparator constituting the PLL circuit.

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