JPH06284000A - Adaptive controller - Google Patents

Abstract

PURPOSE:To lock the phase and frequency deviation of a synchronizing signal in the period as long as they are within a window on condition that the correct synchronizing signal is detected although the synchronizing signal is not detected for >=1 frame by gating the detected synchronizing signal with a window signal, obtaining a signal based upon the synchronizing signal and window signal according to whether or not the synchronizing signal is correct, and comparing in phase the signal with the frame signal from a 1/N counter by a phase comparing circuit. CONSTITUTION:This adaptive controller has a synchronism detecting circuit 22 which detects synchronism, a VCO 29, the 1/N counter 30 which obtains a frequency-divided signal of frequency in 1/N of the output, a decoder 31 which generates the window signal on the basis of the frequency-divided signal, a decision circuit 32 which detects whether or not the synchronizing signal is from a transmission source by using the window signal, the phase comparing circuit 25 which compares with the phase of the frequency-divided signal from the 1/N counter 30, and a reference input control circuit 24 which supplies the signal based upon the synchronizing signal and window signal therefor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for application to, for example, an infrared conference system or the like in which a plurality of signals are transmitted from one master to a plurality of slaves by time division multiplex modulation transmission using infrared rays. Adaptive control device.

[0002]

2. Description of the Related Art Conventionally, as an adaptive control device, for example, an infrared conference for performing time division multiplex transmission by pulse position modulation (PPM) of a plurality of signals from at least one master device to a plurality of slave devices by using infrared rays. A system has been proposed.

In this infrared conference system, data is transmitted by frame synchronization as shown in FIG. 4, for example. That is, in the infrared conference system, the information supplied from the master unit is the synchronization signal pw1 having a pulse width of 800 ns and the pulse position modulation signal having a pulse width of 300 ns that follows. As the time domain, as shown in FIG. 4B, the time until the fall of the synchronization signal pw1 shown in FIG. 4A is the time domain, and the time domain next to this synchronization domain is the blank area BL.
K, and the pulse position modulation signal p from this area onward.
Each w2 has a channel region of 1ch to 13ch, and the last is a blank region BLK. The above is one frame period.

As a phase comparison circuit and a charge pump in the PLL of the slave unit for receiving the information transmitted by the transmission system as shown in FIG. 4, there is one as shown in FIG. 5, for example. Hereinafter, the phase comparison circuit and the charge pump used in the slave unit of the conventional infrared conference system will be described with reference to FIG.

In FIG. 5, reference numeral 1 denotes an input terminal to which a reception synchronization signal from a receiver circuit of a slave unit of an infrared conference system (not shown) is supplied. The input terminal 1 is connected to one input terminal of a NAND circuit 2. The other input terminal of the NAND circuit 2 is connected to the output terminal of the NAND circuit 3, and the output terminal of the NAND circuit 2 is connected to the input terminal of the NAND circuit 3 and one of the NAND circuits 4 constituting the latch circuit. It is connected to the input terminal and the input terminal of the NAND circuit 11.

The other input terminal of the NAND circuit 4 is connected to the output terminal of the NAND circuit 5, and the output terminal of this NAND circuit 4 is one input terminal of the NAND circuit 5, the input terminal of the NAND circuit 3 and the NAND circuit 11. NAND circuit 5 connected to each input terminal
The other input end of the NAND circuit 6 is connected to one input end of the NAND circuit 6 and the other input end of the NAND circuit 6 is connected to the output end of the NAND circuit 7,
The output terminal of the NAND circuit 10 is the input terminal of the NAND circuit 10 and the NAND circuit 11
Of the NAND circuit 7 and the other input terminal of the NAND circuit 7 is connected to the output terminal of the NAND circuit 9.

Reference numeral 8 is an input terminal to which a reference frame signal is supplied from a signal processing circuit of a slave unit of an infrared conference system (not shown). This input terminal 8 is connected to an input end of a NAND circuit 9 and the NAND circuit 9 has an input terminal. The other input terminal is connected to the output terminal of the NAND circuit 10, and the output terminal of the NAND circuit 9 is connected to the input terminal of the NAND circuit 11 and the input terminal of the NAND circuit 10.

The input end of the NAND circuit 3 and the input end of the NAND circuit 10 are connected, and the connection point is the NAND circuit 1.
1, the other input end of the NAND circuit 5 and the other input end of the NAND circuit 6 are connected, and the connection point is connected to the connection point of each input end of the NAND circuits 3 and 10.

The output terminal of the NAND circuit 10 is connected via an inverter 12 to the gate of an N-channel MOSFET 13 which constitutes a charge pump.
Is connected to the gate of the P-channel MOSFET 14. The source of the P-channel MOSFET 14 that constitutes this charge pump is connected to the power supply terminal 15 to which the power supply voltage is supplied, and the P-channel MOSFET 1
The drain of the N-channel MOSFET 13 is connected to the drain of the N-channel MOSFET 13, and the source of the N-channel MOSFET 13 is grounded. And these P channel MOSF
Drain of ET14 and N-channel MOSFET 13
The output terminal 16 is derived from the connection point between the drains of the.

The operation of the phase comparison circuit and charge pump shown in FIG. 5 will be described with reference to FIG.

First, as shown in FIG. 6A, when a synchronizing signal is supplied from a receiving circuit (not shown) and a reference frame signal is supplied from a signal processing circuit (not shown), the NAND circuit 3 is supplied as shown in FIG. 6C. 6D is obtained, and the NAND circuit 10 obtains an output as shown in FIG. 6D. The output of the charge pump is as follows.

That is, when the output from the NAND circuit 3 is at low level "0" and the output from the NAND circuit 10 is at high level (inverted by the inverter 12) "1" (the gate of the N-channel MOSFET 13 is at low level "." 0 "is supplied), the gate potential of the P-channel MOSFET 14 becomes lower than the source potential, so that the P-channel MOSFET 14 is turned on, while the gate potential of the N-channel MOSFET 13 is not higher than the source potential. The N-channel MOSFET 13 is turned off. Therefore, as shown in FIG. 6E, the phase detection signal (high level “1”) is output from the output terminal 16.

On the other hand, when the output from the NAND circuit 3 is high level "1" and the output from the NAND circuit 10 is high level "1" (when low level "0" is supplied to the gate of the N-channel MOSFET 13). Indicates that the P-channel MOSFET 14 is turned off because the gate potential of the P-channel MOSFET 14 is not lower than the source potential, while the N-channel MOSFET 13 is turned off because the gate potential of the N-channel MOSFET 13 is not higher than the source potential. . Therefore, FIG.
As shown in, the output state of the output terminal 16 becomes a high impedance state.

Next, the output from the NAND circuit 3 is at a high level "1" (when a sync signal is not detected in the figure) and the output from the NAND circuit 10 is at a low level "0" (when a sync signal is not detected in the figure). ) (N-channel MOSFET1
When high level "1" is supplied to the gate of 3),
Since the gate potential of the P-channel MOSFET 14 does not become lower than the source potential, the P-channel MOSFE
T14 turns off, while N-channel MOSFET
Since the gate potential of 13 becomes higher than the source potential, the N-channel MOSFET 13 is turned on. Therefore,
As shown in FIG. 6E, the phase detection signal (low level “0”) is output from the output terminal 16.

After that, when the sync signal is detected again, the output from the NAND circuit 3 is at the high level "1" (in the figure, at the time of the next detection when the sync signal is not detected), the NAND circuit 1
When the output from 0 is high level “1” (in the figure, at the time of the next detection when the sync signal is not detected) (N-channel MOSF
When a low level "0" is supplied to the gate of ET13), the potential of the gate of the P-channel MOSFET 14 does not become lower than the potential of the source thereof, so the P-channel M
OSFET14 is turned off, while N channel MO
Since the gate potential of the SFET 13 does not become higher than the source potential, the N-channel MOSFET 13 is also turned off. Therefore, as shown in FIG. 6E, the output of the output terminal 16 is in a high impedance state.

While the sync signal is being reliably supplied, FIG.
As shown in C, the output of the NAND circuit 3 is at low level "0" from the fall of the sync signal shown in FIG. 6A to the fall of the reference frame signal shown in FIG. 6B.
The output of the NAND circuit 10 also becomes a high level “1” as shown in FIG. 6D. In this case, the phase difference detection output from the output terminal 16 becomes a normal output as shown in FIG. 6E.

This output is supplied to a VCO (voltage controlled oscillator) (neither is shown) via, for example, a low pass filter. The VCO outputs the reference frame signal based on the phase difference detection output, and the VCO is phase locked to the transmitted synchronization signal. As a result, after phase locking, for example, the pulse position modulated transmission data from the master unit can be channel selected and demodulated.

[0018]

By the way, in a system for transmitting information by infrared rays as described above, when the transmission line is disturbed or the signal level is attenuated, the phase comparison circuit shown in FIG. It will not operate normally, and the output of the charge pump will not be normal. This will be described with reference to FIG. 6 again.

That is, for example, if the transmission line is disturbed or the signal level is attenuated, the sync signal is not supplied or cannot be detected as shown in FIG. 6A. In this case, as shown in FIG. 6C, the output of the NAND circuit 3 remains at the high level “1”, and as shown in FIG. 6D, the output of the NAND circuit 10 is the reference when the synchronization signal is not supplied. The low level becomes “0” at the fall of the frame signal (FIG. 6B). Therefore, as shown in FIG. 6E, once the synchronization signal cannot be detected, even if the synchronization signal is detected thereafter, for example, if the actual phase difference output is α, it becomes 2π−α and the frequency becomes However, there is a problem in that it moves in a direction of lowering, frame synchronization cannot be obtained, pulse position modulated transmission data cannot be demodulated, channel selection cannot be performed, and normal transmission data reception cannot be performed.

The present invention has been made in view of the above point, and when the transmitted synchronizing signal is used as the reference of the PLL, the fluctuation of the frequency can be suppressed even if the synchronizing signal cannot be detected. It is intended to propose an adaptive control device capable of performing various data transmissions.

[0021]

According to the present invention, a sync signal extracting means 22 for extracting a sync signal in input information and a first frequency division signal for obtaining a first frequency division signal having a frequency of 1 / N of the input signal are provided. A position detecting signal for generating a position detecting signal for detecting the position of the extracted synchronizing signal from the synchronizing signal extracting unit 22 based on the frequency dividing unit 30 and the first divided signal from the first frequency dividing unit 30. Phase comparison between the generation means 31 and the detection means 32 for detecting whether or not the extracted synchronization signal from the synchronization signal extraction means 22 is the synchronization signal from the transmission source by using the position detection signal from the position detection signal generation means 31. Reference signal output means 29 for outputting a reference signal based on the output from the means 25, first frequency-divided signal from the first frequency-dividing means 30, position detection from the synchronizing signal and position-detection signal generating means 31. Perform phase comparison with the signal based on the signal A phase comparison means 25, to the phase comparison means 25, based on the detection signal from the detection means 32,
The control means 24 supplies a signal based on the sync signal and the position detection signal from the position detection signal generating means 31.

Further, according to the present invention, a synchronizing signal extracting means 22 for extracting a synchronizing signal in the input information, and a first dividing means 30 for obtaining a first divided signal having a frequency of 1 / N of the input signal, Position detection signal generating means 31 for generating a position detection signal for detecting the position of the extracted synchronizing signal from the synchronizing signal extracting means 22 based on the first divided signal from the first dividing means 30; 1 of the first frequency division signal from the first frequency division means 30
Second frequency dividing means 3 for obtaining a second frequency-divided signal having a frequency of / M.
6, and a detection means 32 for detecting whether or not the extracted synchronization signal from the synchronization signal extraction means 22 is a synchronization signal from the transmission source by using the position detection signal from the position detection signal generation means 31.
Phase comparison means 25 for performing phase comparison between the first frequency-divided signal from the first frequency-division means 30 and the signal based on the position detection signal from the synchronization signal and position detection signal generation means 31, and this phase comparison The reference signal output means 29 for outputting a reference signal based on the output from the means 25, and the detection rate of the synchronization signal in the input information based on the extraction signal from the synchronization signal extraction means 22 and the detection signal from the detection means 32. Obtaining detection rate calculation means 3
3, 34, addition control means 35, 37, 38 for adding a predetermined value to the previous addition value based on the calculation results from the detection rate calculation means 33, 34, and the addition control means 3
Judgment means 39 for judging the phase locked state and the input level based on the outputs from 5, 37 and 38, and this judgment means 39.
And a control means 24 for supplying a signal based on the position detection signal from the synchronization signal and the position detection signal generation means 31 to the phase comparison means 25 based on the judgment result from the detection means from the detection means 32. It is a thing.

Further, according to the present invention described above, the synchronizing signal is detected from the input information transmitted by infrared rays from the transmission source and received by receiving the infrared rays.

[0024]

According to the structure of the present invention described above, the synchronizing signal in the input information is extracted by the synchronizing signal extracting means 22, and the first frequency division of the frequency of 1 / N of the reference signal from the reference signal outputting means 29 is performed. The signal is obtained by the first frequency dividing means 30, and is extracted from the synchronizing signal extracting means 22 which is generated by the position detection signal generating means 31 based on the first frequency dividing signal from the first frequency dividing means 30. Using the position detection signal for detecting the position of the synchronization signal, the detection means 32 detects whether the extracted synchronization signal from the synchronization signal extraction means 22 is the synchronization signal from the transmission source, and the first frequency division means. The detection signal from the detection means 32 is supplied to the phase comparison means 25 which compares the phase of the first frequency-divided signal from 30 and the signal based on the synchronization signal and the position detection signal from the position detection signal generating means 31. Based on the synchronization signal and position detection signal generating means 31 A signal based on a position detection signal supplied by the control unit 24.

According to the above-described structure of the present invention, the synchronizing signal in the input information is extracted by the synchronizing signal extracting means 22, and the first component of the frequency of 1 / N of the reference signal from the reference signal outputting means 29 is extracted. The frequency dividing signal is obtained by the first frequency dividing means 30, and the synchronizing signal extracting means 22 generates the position detecting signal generating means 31 based on the first frequency dividing signal from the first frequency dividing means 30. Using the position detection signal for detecting the position of the extracted sync signal, the detection means 32 detects whether the extracted sync signal from the sync signal extraction means 22 is the sync signal from the transmission source,
Extraction signal from synchronization signal extraction means 22 and detection means 32
Based on the calculation result from the detection rate calculation means 33, 34 that obtains the detection rate of the synchronization signal in the input information based on the detection signal from, the addition control means 35, 3 adds a predetermined value to the previous addition value.
7, 38, and the addition control means 35, 37, 38
The judgment means 39 judges the phase locked state and the input level based on the output from the judgment means 39. Based on the judgment result from the judgment means 39, the phase comparison means 25 receives the synchronization signal and the sync signal from the detection signal from the detection means 32. Position detection signal generating means 31
The control means 24 supplies a signal based on the position detection signal from.

Further in the above, according to the configuration of the present invention,
The infrared signal is transmitted from the transmission source, and the synchronizing signal is detected from the input information obtained by receiving the infrared ray through the above-described processes.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the adaptive control circuit of the present invention is applied to, for example, an infrared conference system will be described in detail below with reference to FIG.

For convenience of description, the structure related to a general loop until phase locking will be described. In FIG. 1, reference numeral 20 denotes a light receiver for receiving transmission data output as infrared rays from a light emitter of the master device, which is pulse position modulated (PPM), not shown, for example, and is received by the light receiver 20. The infrared light is photoelectrically converted into a pulse position modulation signal at the time of transmission, and then supplied to the synchronization detection circuit 22 and the gate circuit 40 via the amplifier circuit 21.

The synchronization detection circuit 22 extracts a synchronization signal from the pulse position modulation signal from the amplifier circuit 21 and supplies the extracted synchronization signal to the window control circuit 23. The window control circuit 23 performs gate processing on the synchronization signal from the synchronization detection circuit 22 with a window signal having a frame period described later based on a control signal from a state determination circuit 39 described later. The synchronizing signal gated in the window control circuit 23 is supplied to the reference input control circuit 24.

The reference input control circuit 24 includes a gated synchronization signal from the window control circuit 23, a window signal from a decoder 31 described later, and a determination circuit 3 described later.
Based on the determination signal from 2, the input control of the synchronization signal and the window signal to the phase comparison circuit 25 is performed. The phase comparison circuit 25 is supplied with a signal based on the synchronization signal and the window signal at one input terminal thereof, and the 1 / N counter 30 to be described later is provided.
When the frequency-divided signal from (which is a 1 / N frequency-divided signal of the output of the VCO 29 described later) is supplied to the other input terminal, the phases of the signals supplied to these two input terminals are compared,
The phase comparison signals are output from the one and the other output terminals, respectively. Both of the phase detection signals are supplied to the PD (phase detection) output control circuit 26.

The PD output control circuit 26 responds to the phase comparison signal from the phase comparison circuit 25 based on the judgment signal from the judgment circuit 32 and outputs the 3-state output charge pump circuit 2.
Output control to 7 is performed. That is, when the PLL is locked, the output from the phase comparison circuit 25 is supplied to the charge pump circuit 27.
To the output of the comparator, and when the PLL is unlocked, the output of the comparator remains unchanged. The charge pump circuit 27 obtains a phase detection signal based on the phase comparison signal from the PD output control circuit 26, and supplies this phase detection signal to the VCO 29 via the low pass filter 28.

The VCO 29 generates a reference signal having a frequency 16 times higher than the frequency of one frame, for example, based on the phase detection signal supplied from the charge pump circuit 27 through the low pass filter 28, and the generated reference signal 1 / Supply to the N counter 30. 1 / N counter 30 is VCO2
The reference signal from 9 is divided into 1 / N to obtain a signal having a frame period (hereinafter referred to as a frame signal).
The M counter 36 is supplied to each of them, and the upper several bits of the frame signal are supplied to the decoder 31.

Although the description of the configuration is not complete, the configuration of the system related to the operation in the general loop until the phase is locked and the operation of this loop will be described. First, the synchronization signal detection circuit 22 detects a synchronization signal from the signal of the time division multiplex transmission, and the detected synchronization signal is supplied to one input terminal of the phase comparison circuit 25. On the other hand, the frame signal obtained by dividing the reference signal from the VCO 29 by the 1 / N counter 30 is input to the other input terminal of the phase comparison circuit 25. The phase comparison circuit 25 operates at the edge of the signal regardless of the duty of the signal, and outputs two phase comparison signals as described above. The charge pump circuit 27 outputs the two phase comparison signals.
Thus, a 3-state phase detection signal is obtained. This phase detection signal is supplied to the VCO 29 via the low pass filter 28, and the VCO 29 generates a reference signal based on the phase detection signal passed through the low pass filter 28. As a result, the phase of the synchronizing signal transmitted is locked.

By the way, in the case where the PLL portion is composed only of the loop constituent circuit described here, if the synchronizing signal cannot be detected, the frequency shifts in the same direction as in the conventional case, and the frame synchronization cannot be achieved. , The pulse position modulated transmission data cannot be demodulated, correct channel selection cannot be performed, and normal transmission data reception cannot be performed.

Therefore, in this example, circuits other than the above-mentioned loop constituent circuits are used so that the pulse position modulation signal cannot be demodulated or the channel cannot be selected when the synchronization signal cannot be detected. That is, since the frame is synchronized when the PLL is locked, the protection circuit (PLL circuit other than the loop described above) is operated once locked.
By temporarily breaking the loop, the factor that lowers the frequency is removed.

What is necessary for the operation as the protection circuit is the processing by the reference input control circuit 24, the PD output control circuit 26, the judgment circuit 32 and the decoder 31 shown in FIG. Become. The operation of these circuits will be described with reference to FIG.

First, the case where the sync signal can be detected will be described. The time domain is synchronous SYNC as shown in FIG. 2A.
In the case of blank BLK, first, the synchronization detection circuit 22 detects a synchronization signal as shown in FIG. 2B. On the other hand, the 1 / N counter 30 is
The output from 9 is counted to obtain a frame signal as shown in FIG. 2C, and this frame signal is supplied to the phase comparison circuit 25 and the 1 / M counter, respectively.

The upper few bits of the counter output from the 1 / N counter 30 are supplied to the decoder 31. The decoder 31 decodes the upper few bits of the output from the 1 / N counter 30 and uses the decoded data as a channel gate signal in a channel gate distribution circuit (CG) 4
Supply to 0b.

The channel gate distribution circuit 40b is based on a channel address (for example, data corresponding to a channel manually set by the user, channels 1 to 13 in the PPM format) from a main circuit (not shown) via the input terminal 40a. Then, the data from the decoder 31 is distributed and supplied to the gate circuit 40. The gate circuit 40 gates the received signal from the amplifier circuit 21 based on each output from a state determination circuit 39 and a channel gate distribution circuit 40b which will be described later. That is, the channel gate signal that becomes active only in the time domain of the channel selected by the user is decoded from the 1 / N counter 30, so that the demodulation circuit 41 demodulates only the received signal of the channel selected by the user. To

The decoder 31 has a 1 / N counter 30.
2D is decoded to obtain the window signal shown in FIG. 2D, and the window signal is supplied to the window control circuit 23, the reference input control circuit 24, and the determination circuit 32, respectively. As described above, the window control circuit 23 performs gate processing on the synchronization signal from the synchronization detection circuit 22 with this window signal.
The synchronization signal in the window signal is likely to be a stochastic correct synchronization signal. Therefore, as shown in FIG. 2E, the determination circuit 10 makes a determination based on the synchronization signal and the window signal (FIG. 2D), and at the rising edge of the synchronization signal shown in FIG. 2B, as shown in FIG. The determination signal indicating that the signal is correct is set to high level "1". still,
This determination signal is set to the low level "0" by the signal from the decoder 31 at the blank position in the time domain shown in FIG. 2E.

On the other hand, the reference input control circuit 24 is the judgment circuit 3
While the judgment signal from 2 is low level "0", the decoder 3
The window signal from 1 is supplied to one input terminal of the phase comparison circuit 25, and when the determination signal from the determination circuit 32 becomes the high level "1", the gated synchronization signal from the window control circuit 23 is phased. It is supplied to one input terminal of the comparison circuit 25. The signal supplied to one input terminal of the phase comparison circuit 25 is shown in FIG. 2F. As shown in FIG. 2F, the input to one input terminal of the phase comparison circuit 25 becomes a high level “1” at the rising edge of the window signal shown in FIG. 2D, and thereafter, the determination from the determination circuit 32 shown in FIG. 2E. When the signal becomes the high level "1", the detection synchronization signal shown in FIG. 2B becomes the high level "1" during the high level "1", and the detection signal becomes the low level "0" and the low level "0". "become.

1 is input to the other input terminal of the phase comparison circuit 25.
The frame signal (see FIG. 2C) from the / N counter 30 is supplied. Therefore, the phase comparison circuit 25 compares the phase of the frame signal shown in FIG. 2C with the phase of the input signal shown in FIG. 2F, and as a result, the phase comparison signal shown in FIG. 2G and the phase comparison signal shown in FIG. It is output, and this is supplied to the PD output control circuit 26.

Here, the PD output control circuit 26 is configured as shown in FIG.
The decision signal from the decision circuit 32 shown in FIG.
In the case of, the two phase comparison signals are supplied to the charge pump circuit 27. In the charge pump circuit 27,
Based on the phase comparison signal from the PD output control circuit 26, FIG.
A phase detection signal as shown by I is output. Then, this phase detection signal is passed through the low pass filter 28 to the VCO 2
Then, as described above, the VCO 29 outputs the reference signal having the frequency based on the phase detection signal, and shifts to the phase locked state.

Next, the case where the sync signal cannot be detected will be described with reference to FIG. Explaining the case where the time domain is the sync SYNC and the blank BLK as shown in FIG. 3A, first, the sync signal from the sync detection circuit 22 is at the window position of the window signal as shown in FIGS. 3B and 3D. Absent. Therefore, no synchronization signal is output from the window control circuit 23. On the other hand, the 1 / N counter 30
3C supplies a frame signal as shown in FIG. 3C to the phase comparison circuit 25 and the 1 / M counter 36, respectively.
The counter output from the / N counter 30 is supplied to the decoder 31.

The decoder 31 decodes the counter output from the 1 / N counter 30 to obtain the window signal shown in FIG. 3D, and the window signal is used as the window control circuit 2.
3, the reference input control circuit 24 and the determination circuit 32 are supplied respectively. As shown in FIG. 3E, the determination circuit 10 makes a determination based on the synchronization signal and the window signal (FIG. 3D) from the window control circuit 23.

However, in this example, FIG.
Since the detection synchronization signal shown in FIG. 3B does not enter the window signal shown in FIG. 3, the determination circuit 10 does not set the determination signal to the high level "1" indicating that the detection synchronization signal is correct, as shown in FIG. 3E. .

On the other hand, the reference input control circuit 24 is the judgment circuit 3
Since the determination signal from 2 remains low level "0", the window signal from the decoder 31 is continuously supplied to one input terminal of the phase comparison circuit 25. The signal supplied to one input terminal of the phase comparison circuit 25 is shown in FIG. 3F. As shown in FIG. 3F, the input to one input terminal of the phase comparison circuit 25 becomes high level “1” at the rising edge of the window signal shown in FIG. 3D, and thereafter, as shown in FIG. Since the determination signal from 1 remains low level "0", the window signal shown in FIG. 3D becomes high level "1" while the window signal is high level "1", and this window signal becomes low level "0". , Becomes low level “0”.

1 is applied to the other input terminal of the phase comparison circuit 25.
A frame signal (see FIG. 3C) from the / N counter 30 is supplied. Therefore, in the phase comparison circuit 25, the phase of the frame signal shown in FIG. 3C is compared with the phase of the input signal shown in FIG. 3F, and as a result, the phase comparison signal shown in FIG. 3G and the phase comparison signal shown in FIG. It is output, and this is supplied to the PD output control circuit 26.

Here, the PD output control circuit 26 operates as shown in FIG. 3E.
The decision signal from the decision circuit 32 shown in FIG.
In the case of, the two phase comparison signals are not supplied to the charge pump circuit 27. Therefore, the phase detection signal is not output from the charge pump circuit 27 as shown in FIG. 3I.
In this state, as described above, the PLL temporarily breaks the loop, that is, the PD output control circuit 2
Reference numeral 6 disconnects the loop when the PLL is locked and operates the comparator when the PLL is unlocked. That is, PL
When L is unlocked, a general PLL loop is used, and when locked, adaptive control described later is performed.

With this, it is possible to eliminate the factor of moving the frequency to the lower side, and even if the sync signal is not detected for one frame or more, if the correct sync signal can be detected, the phase and frequency shift between them can be detected. It can be locked if the signal is in the window. Further, in the infrared transmission, a pulse equivalent to the sync signal may be generated in a time region other than the correct sync signal due to the influence of light, especially infrared rays generated by an inverter type fluorescent lamp or the like, which disturbs synchronization 1. This was one of the causes, but it can be prevented with a very high probability.

However, on the contrary, since the above-mentioned window is used for the limitation, the PLL can be locked when the phase or frequency shifts as the correct sync signal exists outside the window in terms of time. In addition to disappearing, the temporal position of the phase detection signal is limited only to the window range, and it becomes impossible to make the unlock determination.

Therefore, in this example, as shown in FIG. 1, an asynchronous detection rate circuit 33, a synchronous detection rate circuit 34,
Addition value control circuit 35, 1 / M counter 36, addition circuit 3
7, a register 38 and a state determination circuit 39 are provided to perform adaptive control according to the detection rate of the synchronization signal.

First, the asynchronous detection rate circuit 33 obtains an asynchronous detection rate based on the detection synchronization signal from the synchronization detection circuit 22, the determination signal from the determination circuit 32, and the frequency division signal from 1 / M, and this data is obtained. It is supplied to the addition value control circuit 35. That is, the asynchronous detection rate is the number of frames in which at least one pulse equivalent to the synchronization signal exists outside the window and there is no synchronization signal in the window in the same frame. The 1 / M counter 36 divides the frame signal from the 1 / N counter 30 by M times to obtain a M times divided signal, and the timing of the register 38 is controlled by this divided signal. The operation is two's complement, and addition and subtraction are performed using an adder.
The initial value is "0", and the initialization is performed by the state determination circuit 39.

On the other hand, the synchronization detection rate circuit 34 includes the determination circuit 3
The high level "1" pulses of the determination signal from 2 are counted, and the detection rate of the synchronization signal is obtained for each cycle of the divided signal from the 1 / M counter. To obtain this detection rate, the determination circuit 32
It can be easily obtained by counting the high level "1" pulses of the determination signal from. This detection rate data is supplied to the addition value control circuit 35.

The added value control circuit 35 is the asynchronous detection rate circuit 3
Based on the asynchronous detection rate data from 3 and the synchronous detection rate data from the synchronous detection rate circuit 34, the added value to the adder circuit 37 is controlled. The adder circuit 37 adds the added value from the added value control circuit 35 and the output from the register 38, that is, an appropriate initial value from the state determination circuit 39 in the initial state, and returns the added data to the register 38 again. Supply. Therefore, in the initial state, the register 38 stores the initial value from the state determination circuit 39, but thereafter, the addition data from the sequential addition circuit 37 is stored, and the stored data is again stored in the addition value control circuit 35. Is added to the data from.

The addition data stored in the register 38 is supplied to the state judging circuit 39. This state judging circuit 39 judges the state from the added data from the register 38,
The results are supplied to the window control circuit 23 and the determination circuit 32, respectively, and the window control circuit 23 and the determination circuit 32 are supplied.
To control.

Here, the pulse position modulation signal will be described. The synchronization signal and the pulse position modulation signal have a correlation in detection rate. The pulse position modulation signal cannot be corrected if there is not the total number of samples, but the demodulation side can perform processing such as intermediate value interpolation.

The detection rate has a fixed relationship with the input level, and the pulse position modulation signal also has a correlation with this. Therefore, when the detection rate falls below a certain level, even if the pulse position modulation signal is demodulated, there is no sound. Can not be recognized.

Therefore, by selecting an appropriate value from the detection rate for the above-mentioned added value, it is possible to judge the decrease of the input level, the unlocking of the PLL, and the locking of the PLL. However, in the synchronization detection rate circuit 34, when infrared transmission is disturbed by external light, the number of pulses equivalent to the synchronization signal increases, so the detection rate does not decrease even if the PLL is unlocked, and the determination is made. Can not. Therefore, the asynchronous detection rate circuit 33 that determines that the interference is close by the synchronous detection rate outside the window is required.

As described above, from the detection rate of the sync signal to the PL
The state of L can be determined, and thus the input state can be determined without using the phase detection signal or the input level of the amplifier circuit 21, and the environment of the slave unit (receiver) can be determined. Can be made to judge.

As an application, the calculation result, the value of the detection rate, etc. can be used as a parameter of an attenuator (not shown). The position of the attenuator in FIG. 1 is between the low pass filter 42 and the amplifier circuit 43. Also,
As the simplest form of hardware, for example, if the configuration of the addition value control circuit 35 is a comparator and a distributor and the problem of processing speed is solved, the addition value control circuit 35, the addition circuit 37, the register 38, and the state judgment are performed. The processing of the circuit 39 may be entirely performed by the microcomputer.

Next, the configuration of the audio processing system in the configuration circuit shown in FIG. 1 will be described. The pulse width modulation signal from the amplifier circuit 21 is supplied to the gate circuit 40. As described above, the gate circuit 40 obtains the pulse modulation signal corresponding to the channel selected by the user and supplies the pulse width modulation signal of the designated channel to the demodulation circuit 41. The demodulation circuit 41 demodulates the pulse width modulation signal from the gate circuit 40 to obtain an audio signal, supplies the audio signal to the earphone 44 via the low-pass filter 42 and the amplification circuit 43, and outputs the audio signal from the earphone 44. Let

Next, the operation of the entire child device of the infrared conference system shown in FIG. 1 will be described.

Infrared light from the master unit of the infrared conference system (not shown) is received by the light receiver 20, and the received light is supplied as pulse position modulation signals to the synchronization detection circuit 22 and the gate circuit 40 via the amplifier circuit 21, respectively. . The synchronization detection circuit 22 extracts a synchronization signal from the pulse width modulation signal and supplies the extracted synchronization signal to the window control circuit 23 and the asynchronous detection rate circuit 33, respectively.

In the initial state, the register 38 is initialized to "0" by the state judging circuit 39, and the PLL
Start from the unlocked state. After that, when the output from the register 38 is supplied to the state determining circuit 39, the state determining circuit 39 determines whether the PLL is unlocked or the PLL is locked based on the value, and the determination result is determined by the window control circuit 23 and It is supplied to the determination circuit 32, respectively. The state determination circuit 39 determines whether the PLL is locked or unlocked, and whether the input level is sufficient or insufficient for demodulation. Further, as shown in FIG. 1, a signal is inputted from the state judgment circuit 39 to the gate circuit 40 because the PLL is unlocked or the audio mute is pulsed when it is judged that the input level is insufficient for demodulation. This is because the position-modulated signal is not output. Alternatively, for example, the output from the state determination circuit 39 may be supplied to an attenuator (not shown), and the attenuator level may be set to −∞ dB when the output should be muted.

On the other hand, the window signal obtained by decoding the output from the 1 / N counter 30 is output from the decoder 31, so that the window control circuit 23 outputs from the decoder 31 based on the determination result from the state determination circuit 39. The gate control is performed on the synchronization signal from the synchronization detection circuit 22 with the window signal.

Then, the decision circuit 32 makes a decision based on the decision result from the state decision circuit 39. That is,
The determination circuit 32 determines whether or not the synchronization signal is correct based on the window signal from the decoder 31, the determination result from the state determination circuit 39 and the synchronization signal from the synchronization detection circuit 22, and the determination obtained by this determination The signals are supplied to the reference input control circuit 24 and the PD output control circuit 26, respectively.

The reference input control circuit 24 controls the input supplied to one input terminal of the phase comparison circuit 25 based on the determination result from the determination circuit 32. As a result, when the judgment signal from the judgment circuit 32 is low level “0”, it rises at the rising edge of the window signal, and when the judgment signal from the judgment circuit 32 becomes high level “1”, the synchronization signal falls. It becomes a pulse that falls at.

In the phase comparison circuit 25, the phase comparison between the input pulse of one input terminal and the frame signal supplied from the 1 / N counter 30 to the other input terminal is carried out, and the result is sent to the PD output control circuit 26. Supply. The PD output control circuit 26 controls the output to the charge pump circuit 27 based on the determination signal from the determination circuit 32. The charge pump circuit 27 obtains a phase detection signal based on the output from the PD output control circuit 26. This phase detection signal is supplied to the VCO 29 via the low pass filter 28. As a result, the VCO 29 outputs a signal having a frequency based on the supplied phase detection signal.

When the initial state shifts to the next state (or the initial one block shifts to the next block), the register 38 has a synchronous detection rate circuit 34 and an asynchronous detection rate circuit 3.
Each detection rate data from 3 is supplied to the addition value control circuit 35, whereby the addition circuit 37 adds the value in the period of the first block and the predetermined value from the addition value control circuit 35, and by this addition The obtained addition data is stored again in the register 38, and is used for the state determination processing as described above.

In the audio system, the gate circuit 40
, The pulse position modulated signal is gated by the channel gate signal from the 1 / N counter 31, demodulated by the demodulation circuit 41, and low-pass filtered by the low pass filter 42 to extract the original audio signal. The audio signal is supplied to the earphones 44 via the amplifier circuit 43 and output as audio.

As described above, in this example, the determination circuit 3
In step 2, it is determined whether or not there is a synchronization signal in the window of the window signal to determine whether or not it is a correct synchronization signal. Based on this determination result, the input to the phase comparison circuit 25 is input by the reference input control circuit 24. After control, the phase of this input is compared with that of the frame signal, the synchronous detection rate and the asynchronous detection rate are detected, and the predetermined value is added to the value of the block of the predetermined length based on the detection result. ,
Based on the added value, it is determined whether or not the PLL is locked, and the window control circuit 23 and the determination circuit 32 are controlled based on this determination, so that there is no cause for the frequency to start moving. Even if the sync signal is not detected for one frame or more, if the correct sync signal is detected, the phase and frequency shift between them can be locked within the window, and the PLL can be used from the detection rate without using the phase detection signal. Since the state can be determined, the PLL can be locked even if the phase and frequency shift when the correct synchronization signal is outside the window. Then, for example, in infrared transmission, it is possible to prevent the influence of infrared rays generated from an inverter type fluorescent lamp or the like, for example, the synchronization disturbance caused by the generation of a pulse equivalent to the synchronization signal, with a high probability.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0074]

According to the present invention described above, the synchronizing signal in the input information is extracted by the synchronizing signal extracting means, and the first frequency-divided signal having a frequency of 1 / N of the reference signal from the reference signal outputting means is extracted. The first frequency dividing means, and the position detecting signal generating means generates the first frequency dividing signal based on the first frequency dividing signal from the first frequency dividing means.
Using the position detection signal for detecting the position of the extracted synchronization signal from the synchronization signal extraction means, the detection means detects whether the extracted synchronization signal from the synchronization signal extraction means is the synchronization signal from the transmission source, The detection signal from the detection means to the phase comparison means for performing the phase comparison between the first frequency-divided signal from the frequency-division means 1 and the signal based on the position detection signal from the synchronization signal and the position detection signal generation means. Based on the above, since the control means supplies a signal based on the sync signal and the position detection signal from the position detection signal generating means, there is no cause for the frequency to start moving, and the sync signal is 1 frame or more. Even if it is not detected, if the correct sync signal is detected, the phase between them,
The frequency shift can be locked within the window.

Further, according to the present invention described above, the synchronizing signal in the input information is extracted by the synchronizing signal extracting means, and the first frequency-divided signal having a frequency of 1 / N of the reference signal from the reference signal output means is extracted as the first divided signal. 1 dividing means to obtain the first from the first dividing means
The position detection signal for detecting the position of the extraction synchronization signal generated by the position detection signal generation unit based on the frequency division signal is detected by the detection unit from the synchronization signal extraction unit. From the detection rate calculation means for detecting whether or not the synchronization signal is the synchronization signal from the transmission source and obtaining the detection rate of the synchronization signal in the input information based on the extraction signal from the synchronization signal extraction means and the detection signal from the detection means The addition control means adds a predetermined value to the previous addition value on the basis of the calculation result of, and the determination means determines the phase locked state and the input level based on the output from the addition control means. Based on the determination result from the control means, the phase comparison means supplies the signal based on the position detection signal from the synchronization signal and the position detection signal generation means by the detection signal from the detection means. But If the correct sync signal is detected even if the sync signal is not detected for more than one frame, the phase and frequency deviation during that period can be locked if it is within the window. Since the state of the PLL can be determined without using the phase detection signal, if the correct synchronization signal is outside the window,
The PLL can be locked even if the phase and frequency are shifted.

Further, according to the configuration of the present invention described above,
The infrared signal is transmitted from the transmission source, and the synchronization signal is detected by the above-described processing from the input information obtained by receiving this, so that, for example, in infrared transmission, the influence of infrared rays generated from an inverter type fluorescent lamp, etc. For example, it is possible to prevent, with a high probability, a disturbance in synchronization caused by the generation of a pulse equivalent to the synchronization signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an adaptive control device of the present invention.

FIG. 2 is a timing chart for explaining an embodiment of the adaptive control device of the present invention.

FIG. 3 is a timing chart for explaining an embodiment of the adaptive control device of the present invention.

FIG. 4 is an explanatory diagram showing a time division multiplex transmission format.

FIG. 5 is a configuration diagram showing a phase comparison circuit and a charge pump.

FIG. 6 is a timing chart for explaining operations of a phase comparison circuit and a charge pump.

[Explanation of symbols]

 22 Sync Detection Circuit 23 Window Control Circuit 24 Reference Input Control Circuit 25 Phase Comparison Circuit 26 PD Output Control Circuit 27 Charge Pump Circuit 28 Low Pass Filter 29 VCO 30 1 / N Counter 31 Decoder 32 Judgment Circuit 33 Asynchronous Detection Rate Circuit 34 Sync Detection Rate Circuit 35 Addition value control circuit 36 1 / M counter 37 Addition circuit 38 Register 39 State determination circuit

Claims (3)

[Claims] 1. A synchronization signal extracting means for extracting a synchronization signal in input information, and a first frequency division signal having a frequency of 1 / N of the input signal.
And a position detection signal for generating a position detection signal for detecting the position of the extracted synchronizing signal from the synchronizing signal extracting means based on the first divided signal from the first dividing means. Generating means, detecting means for detecting whether or not the extracted synchronizing signal from the synchronizing signal extracting means is the synchronizing signal from the transmission source by using the position detecting signal from the position detecting signal generating means, and the phase comparing means Based on the output of the reference signal output means for outputting a reference signal, the first frequency division signal from the first frequency division means, the synchronization signal and the position detection signal from the position detection signal generation means. A phase comparison means for performing a phase comparison with the signal, and a signal based on the detection signal from the detection means, based on the synchronization signal or the position detection signal from the position detection signal generation means, for the phase comparison means. Supply Adaptive control apparatus characterized by having a control means. 2. A synchronization signal extracting means for extracting a synchronization signal in input information, and a first frequency division signal having a frequency of 1 / N of the input signal.
And a position detection signal for generating a position detection signal for detecting the position of the extracted synchronizing signal from the synchronizing signal extracting means based on the first divided signal from the first dividing means. Generating means, second dividing means for obtaining a second divided signal having a frequency of 1 / M of the first divided signal from the first dividing means, and the position detecting signal generating means. Detecting means for detecting whether or not the extracted synchronizing signal from the synchronizing signal extracting means is a synchronizing signal from the transmission source using the position detection signal; and a first frequency dividing signal from the first frequency dividing means. Phase comparison means for performing phase comparison with the synchronization signal and a signal based on the position detection signal from the position detection signal generation means, and reference signal output means for outputting a reference signal based on the output from the phase comparison means And the extracted signal from the synchronization signal extraction means and the detection signal. Detection rate calculation means for obtaining the detection rate of the synchronizing signal in the input information based on the detection signal from the means, and adding a predetermined value to the previous addition value based on the calculation result from the detection rate calculation means. The addition control means, the judgment means for judging the phase locked state or the input level based on the output from the addition control means, and the phase comparison means based on the judgment result from the judgment means And a control means for supplying a signal based on the position detection signal from the position detection signal generating means according to the detection signal. 3. The adaptive control device according to claim 1, wherein the input information is transmitted by infrared rays from a transmission source and received by receiving the infrared rays.