JPS5827527B2 - clock circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lock circuit that is suitable for providing multiple functions by making the package terminal rough when there is not enough room for package terminals.

For example, in an LSI, the number of input/output lines is limited depending on the number of package terminals.

Therefore, the problem is how many functions can be achieved using a limited number of terminals.

In particular, with microprocessors (0), the recent trend is toward integrating a memory card, memory card, etc. in addition to a CPU function on one chip, and the relationship between functions and number of terminals has become an important issue. There is.

By the way, one chip or two chips aiming at cost reduction
Chip microcomputers are no exception, with clock circuits on-chip.

0) In a lock circuit like this, the main components are an oscillation circuit and a frequency dividing circuit that are controlled by an external crystal, and some also have a variable frequency dividing ratio that is switched by a signal from a mode terminal. .

FIG. 1 is a block diagram showing such a conventional clock circuit.

In the figure, 1 and 2 are terminals for connecting the crystal resonator, 3
4 is a mode terminal, 4 is a crystal-controlled oscillation circuit, 5 is a frequency division clock generation circuit, 6 is an N frequency division circuit, γ is a switching circuit, 8 is a two-phase clock generation circuit, and Xtal is a crystal oscillator.

The operation of this circuit is as follows.

That is, the oscillation frequency f is between the terminals 1° and 2.

By connecting a crystal oscillator Xtal and causing the oscillation circuit 4 to oscillate, a clock pulse with a period of 0 is obtained.

Frequency division clock generation circuit (1) 5 generates a two-phase frequency division clock pulse to be applied to N frequency division circuit 6 using the (0) clock pulse.

The N frequency divider circuit 6 generates a clock pulse of N periods. Ru.

The switching circuit 7 has the function of switching and sending out the original oscillation θ clock pulse with period θ and the divided clock pulse O with N period 0), and the switching can be done manually from the mode terminal 3. It is done by a signal.

That is, when the input to the mode terminal 3 is at the "H" level (high level), the output of the switching circuit 1 is a clock pulse with a ± period, and the input to the mode terminal 3 is at the "L" level.
'' level (low level), the output of the switching circuit I is a periodic clock pulse.

The output of the switching circuit 1 is converted by the two-phase clock generation circuit 8 into two-phase clock signals φ1° and φ2 that do not overlap with each other.

This clock signal φ1. In addition to being used as an internal timing signal of the microprocessor, φ2 can also be used as a timing signal of peripheral circuits.

As can be seen from the above explanation, in the clock circuit of FIG. 1, the DC level at the mode terminal 3 can be set to H'' or 'L'' to change the frequency division ratio, that is, change the timing period. can.

Now, although the circuit of FIG. 1 is extremely useful, it can only change the period of its clock signal.

However, it would be extremely convenient if the pulse width of the clock signal could be changed.

To realize this, necessary circuits may be added and selected and used as appropriate.

However, considering that the clock circuit is on-chip and that the number of package terminals is limited as described above, this is not an easy problem to solve.

The present invention uses the mode terminal 3 shown in FIG. 1 not only in a direct current manner as in the past, but also in a pulsed manner, and by adding some circuits, the mode terminal 3 can be used only in the period of the clock signal. The present invention provides a clock circuit in which the pulse width can also be changed, and this will be explained in detail below.

FIG. 2 is a block diagram of one embodiment of the present invention, in which the same parts as those described with respect to FIG. 1 are designated by the same symbols.

The illustrated example differs from the conventional example shown in FIG. 1 in that the divided clock generation circuit 5 is controlled by a mode terminal 3, and that a delay circuit 9 is added.

In the embodiment shown in FIG. 2, when the input to the mode terminal 3 is at DC level, the operation is exactly the same as in the conventional example, but the input is a pulse, and depending on the input timing and input pulse width, a two-phase clock is used. The width of the signals φ1° and φ2 can be increased by a unit of .

Although the configuration in each block in FIG. 2 can be modified in many ways, specific examples thereof are shown in FIGS. 3 to 5.

In each figure, the same parts as those explained with reference to FIGS. 1 and 2 are indicated by the same symbols, and the * mark is connected to the respective rotation number.

Fig. 3 shows the oscillation circuit 4, branch clock generation circuit 5, switching circuit 7, and delay circuit 9, Fig. 4 shows the N frequency divider circuit 6, and Fig. 5 shows the two-phase clock generation circuit. Circuit 8 is shown.

In Figure 3, A and B are connection points (nodes), and the signal timing at this point is shown in Figures 7 and 8, and φ and φ' are frequency-divided clock generation points. A two-phase divided clock pulse generated in circuit 5 is applied to divide-by-N circuit 6.

This timing is also shown in FIGS. 7 and 8.

In FIG. 4, the points at which the two-phase divided clock pulses φ and φ' are to be applied are shown.

In FIG. 5, NOL is a non-overlap control circuit, and as seen in FIG.
1. Control is performed so that φ2 does not overlap.

BUF is a buffer circuit. In this embodiment, the mode terminal 3 is normally used with L9 level.

That is, clock signal φ1. The period of φ2 is nine.

Then, when the input of the mode terminal 3 is changed to the HI+ level by B in synchronization with the clock signal φ1, the frequency division clock generation circuit 5 is stopped for one peak, and therefore the N frequency division circuit 6
Since the frequency division of O is not carried out during that time, the output Q
The pulse width of the clock signal φ1 is stretched by 1.

The delay circuit 9 determines the dynamicity of the input to the mode terminal 3.
] The delay time is set in units of -, for example, m×-fof.

There will be a delay.

In that case, if n≦m, the pulse width stretching as described above is performed.

However, when n>m, the switching circuit 71 operates and switches from the N frequency division mode to the 〒 mode.

That is, if the width of the input signal to the mode terminal 3 is less than or equal to mx, the pulse width of the crotter signal φ10) is stretched in proportion to m.

Incidentally, in order to perform trenching using the clock signal φ2, if the input signal at the mode terminal 3 is synchronized with the clock signal φ2, the operation will be exactly the same as described above.

Next, the case where the clock signal φ1 or φ2 is stretched will be described in detail with reference to FIGS. 7 and 8.

FIG. 7 is a timing chart when the clock signal φ1 or φ2 is stretched by 1r.

In the figure, A is the signal timing at point A in Figure 3, which means that the output of the oscillation circuit 4 is also 0, that is,
It is a primary oscillation.

φ and φ' are the timings of the two-phase frequency-divided clock pulses generated by the frequency-divided clock generation circuit 5 in FIG.

3 is the timing of the input signal at the mode terminal 3.

B is the timing of the signal at point B in FIG.
This is the switching circuit 70) output.

φ,. Needless to say, φ2 is the clock signal φ1. φ20
) timing.

It is now assumed that a lock pulse is being sent out from the oscillation circuit 4 as shown in υ)A in FIG.

Then, at the 2rth (or 3rth) mode terminal -3, r, -+ Hj- level Q is applied as shown in Figure 7 θ3.
If one human input signal is applied, the operation of the divided clock generation circuit 5 is prohibited, and the clock pulse φ
, φ' are not sent out as shown by broken lines in FIG.

Therefore, the N frequency divider circuit 6 also does not operate, and therefore the clock signal φ2 is stretched by a width of 1r as shown by hunting.

In the same way (4rth (or 5rth)), when the mode terminal 3 is set to the ``H'' level, the clock signal φ1 is stretched by 1r width.

FIG. 8 is a timing chart when the clock signal φ1 or φ2 is stretched by ITlr width, and the relationship of symbols is the same as in FIG. 7.

Now, as shown in FIG.
I) is stretched mr width.

When the mode terminal 3 is at the T+ HI+ level for more than mr or Q times, the clock pulses φ", φ" in the delay circuit 9
Since there is one circuit stage of 00 shift, the input ■ signal of the mode terminal 3 enters the switching circuit 7, and the output of 〒 appears through *1 to *3.

Clock signal φ1 according to the invention. φ20) The pulse width stretch function can be applied to the following cases.

That is, when interfacing a microprocessor with a memory or Ilo that has a slow access time, it is necessary to fully extend the microprocessor's clock signal to match the low-speed access.

According to the present invention, as is clear from the above,
This can be easily achieved by simply controlling Ti1J of the mode terminal 3.

Also, if the memory is a dynamic memory, it is necessary to periodically refresh the memory cells.

In that case, the cPU must be kept in a halted state during the refresh period.

According to the present invention, if the mode terminal 3 is set to the "H" level when there is a refresh request, the CPU
It is possible to stretch the width of the clock signal for dynamic memory refresh during that period.

When implementing the application example described above, a circuit as shown in FIG. 9 can be used as a circuit for generating an input signal to be applied to the mode terminal 3.

That is, the memory ready request signal (or refresh request signal) is added to one input of the AND circuit 10, and this signal and the clock signal φ2 (
Alternatively, the monostable circuit 11 is operated in synchronization with φ1), and its output sets the mode terminal 3 to the "H" level.

The period is determined by a time limit circuit 12.

As can be seen from the above explanation, according to the present invention, by using mode terminals both statically and dynamically, the number of package terminals can be saved, and only the clock signal θ) frequency division ratio can be reduced. Since the pulse width can also be controlled, it is effective when it is necessary to connect a microprocessor to a low-speed access I10IC, or when using a linear RAM that requires refreshing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, FIGS. 3 to 6 are circuit diagrams showing specific examples of each block in the embodiment of FIG. Figures 7 and 8
The figure is a timing chart for explaining the stretching operation, and FIG. 9 is a circuit diagram showing an example of a circuit that generates an input to be applied to a mode terminal. In the figure, 1 and 2 are terminals, 3 is a mode terminal, 4 is an oscillation circuit, 5 is a frequency division clock generation circuit, 6 is an N frequency division circuit, and 7
8 is a switching circuit, 8 is a two-phase clock generation circuit, 9 is a delay circuit, and Xtal is a crystal resonator.

Claims (1)

[Claims] 1 A mode terminal into which a control signal is input, an oscillation circuit that generates the original oscillation clock pulse, and a frequency division operation that divides the clock pulse from the oscillation circuit and that the control signal is input manually. a frequency divider circuit section that stops, a switching circuit that switches between and transmits the clock pulse from the oscillation circuit and the frequency-divided clock pulse from the frequency divider circuit section, and a switching circuit that switches the clock pulses from the oscillation circuit and the divided clock pulses from the frequency divider circuit section; - Equipped with a two-phase clock generation circuit that converts into a two-phase clock signal that does not wrap, and a delay circuit that receives a signal from a mode terminal, and the delay circuit has a period in which the control signal is continuously input manually. Q) A clock circuit that transmits the output of the miso to the switching circuit to operate the switching circuit.