KR100560565B1 - Device and method for controlling bus possession and data transmission in inter-processor communication block of full electronic exchange - Google Patents

Abstract

The present invention relates to an apparatus and a method for controlling bus occupancy and data transmission in an IPC block of an electronic switching system. In particular, two synchronization clocks having the same phase may be respectively assigned to a bus occupancy / data transmission control unit mounted in a plurality of nodes. The present invention relates to an apparatus and a method for controlling bus occupancy and data transmission in an IPC block of an electronic switch in order to prevent a system malfunction by providing a bus occupancy and data transmission in an IPC block of an electronic switch according to the present invention. According to the controlling device and method, since the 5 MHz bus occupancy reference clock output from the bus occupancy control section and the 20 MHz bus occupancy / data transmission clock output from the synchronization clock generation section are synchronous signals in phase with each other, the bus occupancy / data The transmission control unit performs bus occupancy and data transmission operations by using two signals having the same phase. The system does not malfunction due to the signal, which improves the performance and reliability of the IPC block itself, and the bus occupancy / data transmission control unit uses the 20MHz bus occupancy / data transmission clock of the high frequency band to occupy the bus. Since the data transmission operation is performed, there is an excellent effect that the system processing speed is improved, thereby speeding up the parallel data transmission speed.

Description

DEVICE AND METHOD FOR CONTROLLING BUS POSSESSION AND DATA TRANSMISSION IN INTER-PROCESSOR COMMUNICATION BLOCK OF FULL ELECTRONIC EXCHANGE}             

1 is a functional block diagram showing an apparatus for controlling bus occupancy and data transmission in an IPC block of a conventional all-electronic exchange.

2 is a functional block diagram showing the configuration of an apparatus for controlling bus occupancy and data transmission in an IPC block of an electronic switch according to an embodiment of the present invention;

3 is an operation flowchart illustrating a method of controlling bus occupancy and data transmission in an IPC block of an electronic switch according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: common data bus 100: bus occupancy control unit

200: MINA board 210: synchronous clock generator

220: node 221: bus occupancy / data transmission control unit

The present invention relates to an apparatus and method for controlling bus occupancy and data transmission in an interprocessor communication (IPC) block of an electronic switching system. In particular, a plurality of nodes Apparatus for controlling the bus occupancy and data transmission in the IPC block of the electronic switchboard to prevent system malfunction by supplying two synchronization clocks of the same phase to the bus occupancy / data transmission control unit mounted in the module) It is about a method.

The apparatus for controlling bus occupancy and data transmission in the IPC block of the conventional electronic switchboard includes a bus occupancy control unit 100 'and a plurality of inter-processor communication control devices (MSC IPC Node board Assembly), as shown in FIG. This is referred to as MINA.) It is composed of a clock generation section 210 'mounted in the board 200' and a bus occupancy / data transmission control section 221 'mounted in the plurality of nodes 220', respectively.

Hereinafter, a method of controlling bus occupancy and data transmission in an IPC block of a conventional electronic switchboard will be described with reference to FIG. 1. First, the bus occupancy control unit 100 ′ may include a counter clear signal and a 4 MHz signal. A bus occupancy reference clock is transmitted to the bus occupancy / data transmission control unit 221 'mounted on each of the plurality of nodes 220'. Then, the bus occupancy / data transmission control unit 221 'receives the counter clear signal output from the bus occupancy control unit 100', clears the built-in counter, and outputs 4 from the bus occupancy control unit 100 '. It receives the MHz bus occupancy reference clock and up-counts the built-in counter. Subsequently, the bus occupancy / data transmission control unit 221 'determines whether the number of counting of the built-in counter is its own common data bus occupancy setting number according to a round robin method, thereby determining its own common data bus. If the number of occupancy is set, the common data bus is occupied by using the 10 MHz bus occupancy / data transmission clock output from the clock generator 210 'mounted in the MINA board 200'. Thereafter, the bus occupancy / data transmission control unit 221 'transmits the 10MHz bus occupancy / data transmission clock and parallel data output from the clock generator 210' to another destination node 220 'to which parallel data is to be transmitted. Done.

However, the apparatus and method for controlling bus occupancy and data transmission in the IPC block of the conventional all-electronic exchange described above include a 4 MHz bus occupancy reference clock output from the bus occupancy control section and a 10 MHz bus output from the clock generation section. Since the occupancy / data transmission clocks are asynchronous signals that are out of phase with each other, the 10MHz bus occupancy / data transmission clock when the bus occupancy / data transmission control unit performs bus occupancy and data transmission operations using two signals having different clock sources. There is a problem in that malfunctions often fail to occupy the common bus because they do not recognize the IPC block, resulting in poor performance and reliability of the IPC block itself.

In addition, as an apparatus and method for controlling bus occupancy and data transmission in an IPC block of a conventional all-electronic exchange, a bus occupancy / data transmission control unit uses a 10 MHz bus occupancy / data transmission clock in a low frequency band. Since the occupation and data transmission operations are performed, not only the system processing speed is slowed but also the parallel data transmission speed is slowed.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to prevent a malfunction when a bus occupancy / data transmission control unit in a node performs a bus occupancy and data transmission control operation. An apparatus and method for controlling bus occupancy and data transmission in an IPC block of an electronic switching system are provided.

Another object is that bus occupancy and data transmission within the IPC block of an electronic switchgear for improving bus occupancy and data transmission speed when the bus occupancy / data transmission control in the node performs bus occupancy and data transmission control operations. To provide an apparatus and method for controlling the.

In order to achieve the above object, the apparatus for controlling bus occupancy and data transmission in the IPC block of the electronic switch of the present invention includes a plurality of MINA boards and a common data bus, each of which is equipped with a plurality of nodes in the electronic switch. In one IPC block,

A bus occupancy control unit for transmitting a counter clear signal and a bus occupancy reference clock; Each of the MINA boards is equipped with a bus occupancy reference clock output from the bus occupancy control unit to generate a bus occupancy / data transmission clock multiplied by a frequency multiplied by the same phase as the bus occupancy reference clock. A synchronous clock generation unit for outputting; It is installed in each of a plurality of nodes in the MINA board, and receives a counter clear signal and a bus occupancy reference clock from the bus occupancy controller to clear the built-in counter, and then up-counts the count. When the number of times of common data bus occupancy is set according to the above, the common data bus is occupied by using the bus occupancy / data transmission clock output from the synchronous clock generator, and the bus occupancy / data transmission clock and parallel data are transmitted. Characterized in that it comprises a bus occupancy / data transmission control unit for transmitting to another destination node.

In addition, the method of controlling bus occupancy and data transmission in the IPC block of the electronic switchboard of the present invention is a bus occupancy and data transmission control method using a bus occupancy and data transmission control device mounted in the IPC block of the electronic switchboard. In

A first step of the bus occupancy control unit transmitting a counter clear signal and a bus occupancy reference clock to each of the plurality of MINA boards; The synchronous clock generation unit mounted in each of the plurality of MINA boards receives the bus occupancy reference clock, generates the bus occupancy / data transmission clock multiplied by the frequency while having the same phase as the bus occupancy reference clock. Outputting to a bus occupancy / data transmission control section; A third step of receiving a counter clear signal by the bus occupancy / data transmission control unit respectively mounted in a plurality of nodes, and clearing a built-in counter; A fourth step of the bus occupancy / data transmission control unit receiving a bus occupancy reference clock and up-counting an embedded counter; A fifth step of determining whether the number of counting of the counter is a set number of owned common data bus occupied in a round robin manner; If the number of counting of the counter in the fifth step is not the number of the common data bus occupancy setting according to the round robin method, the process proceeds to the fifth step again, and the counting number of the counter is the own common data according to the round robin method. A sixth step of occupying a common data bus by using a bus occupancy / data transmission clock outputted from the synchronous clock generator if the number of bus occupancy is set; And a seventh step in which the bus occupancy / data transmission control unit transmits a bus occupancy / data transmission clock and parallel data to another destination node to be transmitted.

Hereinafter, an apparatus and method for controlling bus occupancy and data transmission in an IPC block of an electronic switch according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a functional block diagram of an apparatus for controlling bus occupancy and data transmission in an IPC block of an electronic switch according to an embodiment of the present invention. According to FIG. The control unit 100, and a plurality of MINA board 200 and a common data bus (Data Bus) (10), wherein the plurality of MINA board 200 is a synchronization clock generating unit 210 and each It can be seen that it is composed of eight nodes 220, and the plurality of nodes 220 are equipped with a bus occupancy / data transmission control unit 221, respectively.

On the other hand, the apparatus for controlling bus occupancy and data transmission in the IPC block of the electronic switch according to an embodiment of the present invention, as shown in Figure 2, the bus occupancy control unit 100 and a plurality of MINA board (200) The bus occupancy / data transmission control unit 221 mounted in each of the synchronous clock generating unit 210 and the plurality of nodes 220 respectively installed in the C).

The bus occupancy control unit 100 is mounted in an IPC block to transmit a counter clear signal to the bus occupancy / data transmission control unit 221 mounted to each of the plurality of nodes 220, and transmits a 5 MHz bus occupancy reference clock. The synchronous clock generation unit 210 and the bus occupancy / data transmission control unit 221 transmits.

On the other hand, the synchronous clock generator 210 is mounted in each of a plurality of MINA board 200, receives the 5MHz bus occupancy reference clock output from the bus occupancy control unit 100, the 5MHz bus occupancy reference clock It generates the 20MHz bus occupancy / data transmission clock multiplied by four times the frequency while having the same phase as, and then outputs to the bus occupancy / data transmission control unit 221 mounted in each of the plurality of nodes (220) It can be configured using the CY7B991 chip developed by Sipher Corporation.

In addition, the bus occupancy / data transmission control unit 221 is mounted in each of the plurality of nodes 220 mounted in the MINA board 200, and receives a counter clear signal output from the bus occupancy control unit 100 to be incorporated therein. Then, the counter is cleared, and the 5MHz bus occupancy reference clock output from the bus occupancy controller 100 is input to up-count the embedded counter.

Subsequently, the bus occupancy / data transmission control unit 221 determines whether the number of counting of the counter has become its common data bus occupancy setting frequency according to a round robin method, and when the common data bus occupancy setting number is its synchronization, Another destination to occupy the common data bus 10 by using the 20 MHz bus occupancy / data transmission clock output from the clock generator 210 and to transmit the 20 MHz bus occupancy / data transmission clock and parallel data. It serves to transmit to the node 220.

Then, the bus occupancy and data transmission control in the IPC block of the electronic switching system according to an embodiment of the present invention using the apparatus for controlling bus occupancy and data transmission in the IPC block of the electronic switching system having the above configuration. How to do this will be described.

3 is an operation flowchart showing a method of controlling bus occupancy and data transmission in an IPC block of an electronic switch according to an embodiment of the present invention, where S represents a step.

First, the bus occupancy control unit 100 transmits a counter clear signal to the bus occupancy / data transmission control unit 221 mounted to each of the plurality of nodes 220, and generates a 5MHz bus occupancy reference clock. The controller 210 and the bus occupancy / data transmission control unit 221 respectively transmit (S1).

Then, the synchronous clock generating unit 210 receives the 5MHz bus occupancy reference clock output from the bus occupancy controller 100, and has a frequency multiplied by four times with the same phase as the 5MHz bus occupancy reference clock. A MHz bus occupancy / data transmission clock is generated and then output to a bus occupancy / data transmission control unit 221 mounted in each of the plurality of nodes 220 (S2).

Meanwhile, the bus occupancy / data transmission control unit 221 mounted in each of the plurality of nodes 220 receives a counter clear signal output from the bus occupancy control unit 100 to clear the built-in counter (S3).

Thereafter, the bus occupancy / data transmission control unit 221 receives the 5 MHz bus occupancy reference clock output from the bus occupancy control unit 100 to up-count the embedded counter (S4).

Subsequently, the bus occupancy / data transmission control unit 221 determines whether the number of counting of the built-in counter is its own common data bus occupancy setting number according to the round robin method (S5).

In this case, the bus occupancy / data transmission control unit 221 performs the fifth step (S5) if the counting number of the counter is not the number of common data bus occupancy set by the round robin method (NO) again in the fifth step Proceed to (S5). However, the bus occupancy / data transmission control unit 221, if the counting count of the counter in the fifth step (S5) is set to the number of common data bus occupied by the round robin method (YES), the synchronization clock generation unit The common data bus is occupied using the 20 MHz bus occupancy / data transmission clock output from 210 (S6).

Thereafter, the bus occupancy / data transmission control unit 221 transmits the 20 MHz bus occupancy / data transmission clock and parallel data output from the synchronous clock generator 210 to another destination node 220 to which the data is to be transmitted ( S7).

Accordingly, the bus occupancy / data transmission control unit 221 is a 5MHz bus occupancy reference clock output from the bus occupancy control unit 100 which is a signal synchronized with each other and the 20MHz bus occupancy output from the synchronous clock generation unit 210. Bus occupancy and data transmission operations are performed using the data transmission clock, thereby preventing system malfunction due to asynchronous signals.

According to the apparatus and method for controlling bus occupancy and data transmission in the IPC block of the electronic switch according to the present invention as described above, the 5MHz bus occupancy reference clock output from the bus occupancy control section and the sync clock generation section are output. Since the 20MHz bus occupancy / data transmission clocks are synchronous signals in phase with each other, the bus occupancy / data transmission control section performs bus occupancy and data transmission operations using two signals in the same phase, thereby causing a system malfunction due to an asynchronous signal. This does not occur, and there is an excellent effect that the performance and reliability of the IPC block itself is improved.

Another effect is that since the bus occupancy / data transmission control unit performs bus occupancy and data transmission operations using a 20 MHz bus occupancy / data transmission clock in a high frequency band, not only does the system processing speed increase, but also parallelism. The data transmission speed is faster.

Claims (2)

In an IPC block having a plurality of MINA boards and a common data bus each of which is equipped with a plurality of nodes in an electronic switching system, A bus occupancy control unit for transmitting a counter clear signal and a bus occupancy reference clock; The bus occupancy reference clocks respectively mounted in the plurality of MINA boards receive the bus occupancy reference clocks output from the bus occupancy control unit, and generate a bus occupancy / data transmission clock multiplied by a frequency multiplied by the same phase as the bus occupancy reference clocks. A synchronous clock generator for outputting; It is installed in each of a plurality of nodes in the MINA board, and receives a counter clear signal and a bus occupancy reference clock from the bus occupancy controller to clear the built-in counter, and then up-counts the count. When the number of times of common data bus occupancy is set according to the above, the common data bus is occupied by using the bus occupancy / data transmission clock output from the synchronous clock generator, and the bus occupancy / data transmission clock and parallel data are transmitted. An apparatus for controlling bus occupancy and data transmission in an IPC block of an electronic switchgear, characterized in that the bus occupancy / data transmission control unit transmits to another destination node. In the bus occupancy and data transmission control method using a bus occupancy and data transmission control device mounted in an IPC block in an electronic switchgear, A first step of the bus occupancy control unit transmitting a counter clear signal and a bus occupancy reference clock to each of the plurality of MINA boards; The synchronous clock generation unit mounted in each of the plurality of MINA boards receives the bus occupancy reference clock, generates the bus occupancy / data transmission clock multiplied by the frequency while having the same phase as the bus occupancy reference clock. Outputting to a bus occupancy / data transmission control section; A third step of receiving a counter clear signal by the bus occupancy / data transmission control unit respectively mounted in a plurality of nodes, and clearing a built-in counter; A fourth step of receiving, by the bus occupancy / data transmission control unit, a bus occupancy reference clock and up-counting an embedded counter; A fifth step of determining whether the number of counting of the counter is a set number of owned common data bus occupied in a round robin manner; If the number of counting of the counter in the fifth step is not the number of the common data bus occupancy setting according to the round robin method, the process proceeds to the fifth step again, and the counting number of the counter is the own common data according to the round robin method. A sixth step of occupying a common data bus by using a bus occupancy / data transmission clock outputted from the synchronous clock generator if the number of bus occupancy is set; The bus occupancy / data transmission control unit performs a bus occupancy / data transmission in the IPC block of the all-electronic switchboard, wherein the bus occupancy / data transmission control unit transmits the bus occupancy / data transmission clock and the parallel data to another destination node. How to control.

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