KR20000076868A - 층간 절연막 형성 방법 및 반도체 장치 - Google Patents
층간 절연막 형성 방법 및 반도체 장치 Download PDFInfo
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- KR20000076868A KR20000076868A KR1020000013124A KR20000013124A KR20000076868A KR 20000076868 A KR20000076868 A KR 20000076868A KR 1020000013124 A KR1020000013124 A KR 1020000013124A KR 20000013124 A KR20000013124 A KR 20000013124A KR 20000076868 A KR20000076868 A KR 20000076868A
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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Abstract
Description
Claims (17)
- TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제1 농도로 O3을 가스원에 함유하는 화학 기상 증착법으로 형성물(object to be formed) 상에 다공성 SiO2막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물 상에 하지 절연막을 형성하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제1 농도로 O3을 가스원에 함유하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO2막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제1항 또는 제2항에 있어서,상기 다공성막의 형성 후에, TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제2 농도로 O3을 가스원에 함유하는 화학 기상 증착법에 의해 SiO2막이 상기 다공성막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제3항에 있어서,상기 다공성 SiO2막 상의 상기 SiO2막의 형성 후에, 상기 SiO2막의 표면이 CMP법으로 연마되어 평탄화되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제4항에 있어서,상기 SiO2막의 표면이 CMP법으로 연마되어 평탄화된 후에, 피복 절연막이 상기 표면에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물에 Cl(염소) 플라즈마 처리를 수행하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 형성물 상에 다공성 SiO2막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물 상에 하지 절연막을 형성하는 단계와,상기 하지 절연막에 Cl(염소) 플라즈마 처리를 수행하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO2막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제6항 또는 제7항에 있어서,상기 다공성 SiO2막의 형성 후에, TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하는 화학 기상 증착법으로 다공성 SiO2막 상에 제1 절연막을 형성하는 단계와,상기 제1 절연막의 표면을 평탄화하기 위해 상기 표면을 에칭하는 단계를 더 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제8항에 있어서,상기 제1 절연막의 상기 표면을 평탄화한 후에, 피복 절연막이 상기 제1 절연막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 농도로 O3을 가스원에 함유하는 화학 기상 증착법으로 형성물 상에 다공성 SiO2막을 형성하는 단계와,다마신 트렌치(trench)가 상기 형성물에 도달하도록 상기 다공성 SiO2막에 다마신 트렌치를 형성하는 단계와,상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와,금속막을 상기 다마신 트렌치에 매립하는 단계와,상기 금속막 상에 배리어 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물 상에 하지 절연막을 형성하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 농도로 O3을 가스원에 함유하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO2막을 형성하는 단계와,다마신 트렌치가 상기 형성물에 도달하도록 상기 하지 절연막과 상기 다공성 SiO2막에 다마신 트랜치를 형성하는 단계와,상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와,금속막을 상기 다마신 트렌치에 매립하는 단계와,상기 금속막 상에 배리어 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물에 Cl(염소) 플라즈마 처리를 수행하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 형성물 상에 다공성 SiO2막을 형성하는 단계와,다마신 트렌치가 상기 형성물에 도달하도록 상기 다공성 SiO2막에 다마신 트랜치를 형성하는 단계와,상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와,금속막을 상기 다마신 트렌치에 매립하는 단계와,상기 금속막 상에 배리어 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 형성물 상에 하지 절연막을 형성하는 단계와,상기 하지 절연막에 Cl(염소) 플라즈마 처리를 수행하는 단계와,TEOS(테트라에톡시 실란)와 O3을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO2막을 형성하는 단계와,상기 형성물에 도달하도록 다마신 트렌치를 상기 하지 절연막과 상기 다공성 SiO2막에 형성하는 단계와,상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와,금속막을 상기 다마신 트렌치에 매립하는 단계와,상기 금속막 상에 배리어 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제10항 내지 제13항중 어느 한항에 있어서,상기 다마신 트렌치의 형성 후에 상기 다공성 SiO2막과 상기 다마신 트렌치의 측부 및 저부 상에 제2 절연막을 형성함으로써 상기 측벽 절연막이 형성되고, 상기 다마신 트렌치의 측부에 형성된 제2절연막의 부분을 남기도록 상기 제2 절연막에 이방성 에칭을 수행하여, 상기 다마신 트렌치의 저부에서 상기 형성물의 표면을 노출시키는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제10항 내지 제13항중 어느 한항에 있어서,상기 배리어 금속막의 형성 후에, 피복 절연막이 상기 다공성 SiO2막 및 상기 배리어 금속막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제1항, 제2항, 제6항, 제7항, 제10항 내지 제13항중 어느 한항에 있어서,상기 다공성 SiO2막의 형성 후에, H(수소) 플라즈마 처리가 다공성 SiO2막에 수행되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 제1항 내지 제15항중 어느 한항의 방법에 의해 형성된 층간 절연막을 갖는 것을 특징으로 하는 반도체 장치.
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| US6627532B1 (en) | 1998-02-11 | 2003-09-30 | Applied Materials, Inc. | Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition |
| JP4610080B2 (ja) * | 2000-12-25 | 2011-01-12 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| US6472333B2 (en) | 2001-03-28 | 2002-10-29 | Applied Materials, Inc. | Silicon carbide cap layers for low dielectric constant silicon oxide layers |
| DE10134099A1 (de) * | 2001-07-13 | 2002-10-17 | Infineon Technologies Ag | Bedeckung von Leiterbahnen einer integrierten Halbleiterschaltung durch zwei Deckschichten |
| US7247252B2 (en) * | 2002-06-20 | 2007-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of avoiding plasma arcing during RIE etching |
| TW200428470A (en) | 2003-06-05 | 2004-12-16 | Semiconductor Leading Edge Tec | Method for manufacturing semiconductor device |
| DE10350689B4 (de) * | 2003-10-30 | 2007-06-21 | Infineon Technologies Ag | Verfahren zur Erzeugung von Isolatorstrukturen in einem Halbleitersubstrat |
| KR100555539B1 (ko) * | 2003-12-17 | 2006-03-03 | 삼성전자주식회사 | 고밀도 플라즈마 화학기상증착 공정에 의한 갭 충전방법및 그 충전방법을 포함하는 집적 회로 소자의 제조방법 |
| US8053171B2 (en) | 2004-01-16 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Substrate having film pattern and manufacturing method of the same, manufacturing method of semiconductor device, liquid crystal television, and EL television |
| TW200631095A (en) * | 2005-01-27 | 2006-09-01 | Koninkl Philips Electronics Nv | A method of manufacturing a semiconductor device |
| JP5284756B2 (ja) * | 2008-10-31 | 2013-09-11 | 凸版印刷株式会社 | 電源回路及び電源安定化方法 |
| JP2010108360A (ja) * | 2008-10-31 | 2010-05-13 | Elpida Memory Inc | シミュレーション方法、情報処理装置およびプログラム |
| US8524616B2 (en) * | 2008-11-12 | 2013-09-03 | Microchip Technology Incorporated | Method of nonstoichiometric CVD dielectric film surface passivation for film roughness control |
| KR101678040B1 (ko) | 2008-12-04 | 2016-11-21 | 에이에스엠엘 네델란즈 비.브이. | 임프린트 리소그래피 장치 및 방법 |
| KR101081659B1 (ko) | 2010-01-29 | 2011-11-09 | 이병훈 | 병명이 표시되는 혈압기 |
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| RU2439743C1 (ru) * | 2010-05-11 | 2012-01-10 | Государственное образовательное учреждение высшего профессионального образования Томский государственный университет систем управления и радиоэлектроники (ТУСУР) | Способ получения пористого диоксида кремния |
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| US7972941B2 (en) | 2007-07-02 | 2011-07-05 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device |
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| KR100430114B1 (ko) | 2004-05-03 |
| EP1213759A1 (en) | 2002-06-12 |
| JP2000332011A (ja) | 2000-11-30 |
| DE60005875D1 (de) | 2003-11-20 |
| EP1037276A1 (en) | 2000-09-20 |
| TW552639B (en) | 2003-09-11 |
| DE60005875T2 (de) | 2004-05-19 |
| KR100390322B1 (ko) | 2003-07-04 |
| KR20020072259A (ko) | 2002-09-14 |
| EP1037276B1 (en) | 2003-10-15 |
| US6524972B1 (en) | 2003-02-25 |
| JP3827056B2 (ja) | 2006-09-27 |
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