KR102928611B1 - 디바이스, 디바이스 제조 장치, 및 디바이스 제조 방법 - Google Patents

디바이스, 디바이스 제조 장치, 및 디바이스 제조 방법

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Publication number
KR102928611B1
KR102928611B1 KR1020237026101A KR20237026101A KR102928611B1 KR 102928611 B1 KR102928611 B1 KR 102928611B1 KR 1020237026101 A KR1020237026101 A KR 1020237026101A KR 20237026101 A KR20237026101 A KR 20237026101A KR 102928611 B1 KR102928611 B1 KR 102928611B1
Authority
KR
South Korea
Prior art keywords
chip
substrate
deformation
electrodes
probe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020237026101A
Other languages
English (en)
Korean (ko)
Other versions
KR20230145330A (ko
Inventor
다케루 다마리
기요카즈 이토이
다이스케 사쿠라이
Original Assignee
파나소닉 아이피 매니지먼트 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 파나소닉 아이피 매니지먼트 가부시키가이샤 filed Critical 파나소닉 아이피 매니지먼트 가부시키가이샤
Publication of KR20230145330A publication Critical patent/KR20230145330A/ko
Application granted granted Critical
Publication of KR102928611B1 publication Critical patent/KR102928611B1/ko
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07183—Means for monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
KR1020237026101A 2021-02-17 2021-12-10 디바이스, 디바이스 제조 장치, 및 디바이스 제조 방법 Active KR102928611B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021023322 2021-02-17
JPJP-P-2021-023322 2021-02-17
PCT/JP2021/045454 WO2022176341A1 (ja) 2021-02-17 2021-12-10 デバイス、デバイス製造装置、及びデバイス製造方法

Publications (2)

Publication Number Publication Date
KR20230145330A KR20230145330A (ko) 2023-10-17
KR102928611B1 true KR102928611B1 (ko) 2026-02-20

Family

ID=82931383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020237026101A Active KR102928611B1 (ko) 2021-02-17 2021-12-10 디바이스, 디바이스 제조 장치, 및 디바이스 제조 방법

Country Status (4)

Country Link
JP (1) JP7766265B2 (https=)
KR (1) KR102928611B1 (https=)
CN (1) CN116802779A (https=)
WO (1) WO2022176341A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023039A (ja) * 2001-07-05 2003-01-24 Matsushita Electric Ind Co Ltd ボンディングダメージの計測方法
JP2006013074A (ja) * 2004-06-24 2006-01-12 Matsushita Electric Ind Co Ltd 半導体実装装置、半導体実装方法
JP2013051355A (ja) * 2011-08-31 2013-03-14 Fujikura Ltd 貫通配線の検査方法、貫通配線基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005228820A (ja) * 2004-02-10 2005-08-25 Renesas Technology Corp 半導体装置およびその製造方法
JP2007157970A (ja) * 2005-12-05 2007-06-21 Sony Corp ボンディング方法及びボンディング装置
JP2007178311A (ja) * 2005-12-28 2007-07-12 Nidec-Read Corp プローブ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023039A (ja) * 2001-07-05 2003-01-24 Matsushita Electric Ind Co Ltd ボンディングダメージの計測方法
JP2006013074A (ja) * 2004-06-24 2006-01-12 Matsushita Electric Ind Co Ltd 半導体実装装置、半導体実装方法
JP2013051355A (ja) * 2011-08-31 2013-03-14 Fujikura Ltd 貫通配線の検査方法、貫通配線基板の製造方法

Also Published As

Publication number Publication date
JP7766265B2 (ja) 2025-11-10
CN116802779A (zh) 2023-09-22
WO2022176341A1 (ja) 2022-08-25
JPWO2022176341A1 (https=) 2022-08-25
KR20230145330A (ko) 2023-10-17
TW202249234A (zh) 2022-12-16

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