WO2022176341A1 - デバイス、デバイス製造装置、及びデバイス製造方法 - Google Patents

デバイス、デバイス製造装置、及びデバイス製造方法 Download PDF

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Publication number
WO2022176341A1
WO2022176341A1 PCT/JP2021/045454 JP2021045454W WO2022176341A1 WO 2022176341 A1 WO2022176341 A1 WO 2022176341A1 JP 2021045454 W JP2021045454 W JP 2021045454W WO 2022176341 A1 WO2022176341 A1 WO 2022176341A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
substrate
strain
strain sensor
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/045454
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
健 玉利
清一 糸井
大輔 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Priority to KR1020237026101A priority Critical patent/KR102928611B1/ko
Priority to CN202180091869.XA priority patent/CN116802779A/zh
Priority to JP2023500565A priority patent/JP7766265B2/ja
Publication of WO2022176341A1 publication Critical patent/WO2022176341A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07183—Means for monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Definitions

  • a device manufacturing apparatus is a device manufacturing apparatus that manufactures a device that includes a chip bonded via a plurality of bumps and a substrate that faces the chip, and includes a stage that holds the substrate. a holding portion for holding the chip; a pressing portion for pressing the chip against the substrate by driving the holding portion; a first end electrically connected to a strain sensor mounted thereon and penetrating at least one of the chip and the substrate and each connected to a corresponding one of the plurality of bumps; a measuring unit that measures the strain of the strain sensor via probes that are in contact with a plurality of external connection electrodes connected to the respective second ends of a plurality of through electrodes having second ends opposite to each other; , provided.
  • the external connection electrodes 1 are provided on the surface of the chip substrate 5 opposite to the bump 4 side.
  • the material of the external connection electrode 1 is gold, silver, copper, tungsten, or the like.
  • step S8 If no joining abnormality has occurred (step S8, NO), the processes after step S5 are repeated.
  • the device 11 according to the present embodiment does not use a microcircuit for resistance value measurement as in the conventional technology, the path from the probe 42 to the chip substrate 5 can be shortened. Therefore, it becomes difficult for noise generated in the mounting process of the device manufacturing apparatus 19 to enter the path, and deterioration in measurement accuracy of the distortion amount due to noise can be suppressed.
  • the probe 42 is electrically connected to the strain sensor 3 via the external connection electrode 13, the through electrode 12, and the bonding pad 7. Therefore, the measuring section 40 connected to the probe 42 can measure the resistance value of the strain sensor 3 .

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
PCT/JP2021/045454 2021-02-17 2021-12-10 デバイス、デバイス製造装置、及びデバイス製造方法 Ceased WO2022176341A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020237026101A KR102928611B1 (ko) 2021-02-17 2021-12-10 디바이스, 디바이스 제조 장치, 및 디바이스 제조 방법
CN202180091869.XA CN116802779A (zh) 2021-02-17 2021-12-10 设备、设备制造装置以及设备制造方法
JP2023500565A JP7766265B2 (ja) 2021-02-17 2021-12-10 デバイス、デバイス製造装置、及びデバイス製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021023322 2021-02-17
JP2021-023322 2021-02-17

Publications (1)

Publication Number Publication Date
WO2022176341A1 true WO2022176341A1 (ja) 2022-08-25

Family

ID=82931383

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/045454 Ceased WO2022176341A1 (ja) 2021-02-17 2021-12-10 デバイス、デバイス製造装置、及びデバイス製造方法

Country Status (4)

Country Link
JP (1) JP7766265B2 (https=)
KR (1) KR102928611B1 (https=)
CN (1) CN116802779A (https=)
WO (1) WO2022176341A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023039A (ja) * 2001-07-05 2003-01-24 Matsushita Electric Ind Co Ltd ボンディングダメージの計測方法
JP2005228820A (ja) * 2004-02-10 2005-08-25 Renesas Technology Corp 半導体装置およびその製造方法
JP2006013074A (ja) * 2004-06-24 2006-01-12 Matsushita Electric Ind Co Ltd 半導体実装装置、半導体実装方法
JP2007157970A (ja) * 2005-12-05 2007-06-21 Sony Corp ボンディング方法及びボンディング装置
JP2007178311A (ja) * 2005-12-28 2007-07-12 Nidec-Read Corp プローブ

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013051355A (ja) * 2011-08-31 2013-03-14 Fujikura Ltd 貫通配線の検査方法、貫通配線基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023039A (ja) * 2001-07-05 2003-01-24 Matsushita Electric Ind Co Ltd ボンディングダメージの計測方法
JP2005228820A (ja) * 2004-02-10 2005-08-25 Renesas Technology Corp 半導体装置およびその製造方法
JP2006013074A (ja) * 2004-06-24 2006-01-12 Matsushita Electric Ind Co Ltd 半導体実装装置、半導体実装方法
JP2007157970A (ja) * 2005-12-05 2007-06-21 Sony Corp ボンディング方法及びボンディング装置
JP2007178311A (ja) * 2005-12-28 2007-07-12 Nidec-Read Corp プローブ

Also Published As

Publication number Publication date
JP7766265B2 (ja) 2025-11-10
CN116802779A (zh) 2023-09-22
JPWO2022176341A1 (https=) 2022-08-25
KR20230145330A (ko) 2023-10-17
KR102928611B1 (ko) 2026-02-20
TW202249234A (zh) 2022-12-16

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