KR102558635B1 - 반도체 웨이퍼의 국부적인 왜곡의 결정에 기초한 전역적인 웨이퍼 왜곡의 개선 - Google Patents

반도체 웨이퍼의 국부적인 왜곡의 결정에 기초한 전역적인 웨이퍼 왜곡의 개선 Download PDF

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KR102558635B1
KR102558635B1 KR1020190094412A KR20190094412A KR102558635B1 KR 102558635 B1 KR102558635 B1 KR 102558635B1 KR 1020190094412 A KR1020190094412 A KR 1020190094412A KR 20190094412 A KR20190094412 A KR 20190094412A KR 102558635 B1 KR102558635 B1 KR 102558635B1
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semiconductor wafer
wafer
distortion
pattern
pixel
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KR20200015426A (ko
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조슈아 후게
나단 아이피
조엘 에스트렐라
안톤 데빌리어스
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도쿄엘렉트론가부시키가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
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    • H—ELECTRICITY
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    • H—ELECTRICITY
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    • H—ELECTRICITY
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    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
KR1020190094412A 2018-08-03 2019-08-02 반도체 웨이퍼의 국부적인 왜곡의 결정에 기초한 전역적인 웨이퍼 왜곡의 개선 Active KR102558635B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054,725 2018-08-03

Publications (2)

Publication Number Publication Date
KR20200015426A KR20200015426A (ko) 2020-02-12
KR102558635B1 true KR102558635B1 (ko) 2023-07-21

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KR1020190094412A Active KR102558635B1 (ko) 2018-08-03 2019-08-02 반도체 웨이퍼의 국부적인 왜곡의 결정에 기초한 전역적인 웨이퍼 왜곡의 개선

Country Status (5)

Country Link
US (1) US10622233B2 (enExample)
JP (1) JP7118928B2 (enExample)
KR (1) KR102558635B1 (enExample)
CN (1) CN110807273B (enExample)
TW (1) TWI790391B (enExample)

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US10847419B2 (en) * 2018-03-14 2020-11-24 Raytheon Company Stress compensation and relief in bonded wafers
WO2020038642A1 (en) * 2018-08-22 2020-02-27 Asml Netherlands B.V. Metrology apparatus
US11393118B2 (en) * 2019-06-18 2022-07-19 Kla Corporation Metrics for asymmetric wafer shape characterization
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
CN115516383B (zh) * 2020-05-14 2025-09-30 Asml荷兰有限公司 对产品特征使用at分辨率量测的晶片对准方法
US12276922B2 (en) 2020-05-22 2025-04-15 Tokyo Electron Limited Backside deposition tuning of stress to control wafer bow in semiconductor processing
US11637043B2 (en) * 2020-11-03 2023-04-25 Applied Materials, Inc. Analyzing in-plane distortion
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
TW202236117A (zh) * 2021-02-03 2022-09-16 日商東京威力科創股份有限公司 膜厚分析方法、膜厚分析裝置及記錄媒體
JP2024519467A (ja) * 2021-04-27 2024-05-14 アプライド マテリアルズ インコーポレイテッド 半導体処理に関する応力およびオーバーレイ管理
US12469725B2 (en) 2021-06-27 2025-11-11 Delta Design, Inc. Method for determining corrective film pattern to reduce semiconductor wafer bow
US12394618B2 (en) 2021-07-08 2025-08-19 Tokyo Electron Limited Method of adjusting wafer shape using multi-directional actuation films
US12051608B2 (en) * 2021-07-20 2024-07-30 Changxin Memory Technologies, Inc. Method for adjusting wafer deformation and semiconductor structure
US11782411B2 (en) * 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
KR20230048952A (ko) * 2021-10-05 2023-04-12 삼성전자주식회사 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법
US12001147B2 (en) 2021-11-19 2024-06-04 Tokyo Electron Limited Precision multi-axis photolithography alignment correction using stressor film
EP4202551A1 (en) * 2021-12-23 2023-06-28 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
KR20240115253A (ko) * 2021-12-06 2024-07-25 에이에스엠엘 네델란즈 비.브이. 기판에 적용된 층의 기계적 특성을 결정하는 방법, 및 관련 디바이스
WO2023108530A1 (en) * 2021-12-16 2023-06-22 Yangtze Memory Technologies Co., Ltd. Prediction of wafer flatness
US11994807B2 (en) 2022-05-03 2024-05-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
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JP2025516535A (ja) * 2022-05-13 2025-05-30 アプライド マテリアルズ インコーポレイテッド 基板曲率を使用して面外歪みを補償するためのドーズマッピング
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