CN110807273B - 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 - Google Patents

基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 Download PDF

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CN110807273B
CN110807273B CN201910711753.6A CN201910711753A CN110807273B CN 110807273 B CN110807273 B CN 110807273B CN 201910711753 A CN201910711753 A CN 201910711753A CN 110807273 B CN110807273 B CN 110807273B
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wafer
distortion
semiconductor wafer
pattern
backside
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CN110807273A (zh
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乔舒亚·霍格
内森·伊普
乔尔·埃斯特雷拉
安东·德维利耶
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Toxicology (AREA)
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  • Data Mining & Analysis (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
CN201910711753.6A 2018-08-03 2019-08-02 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 Active CN110807273B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054,725 2018-08-03

Publications (2)

Publication Number Publication Date
CN110807273A CN110807273A (zh) 2020-02-18
CN110807273B true CN110807273B (zh) 2024-05-14

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CN201910711753.6A Active CN110807273B (zh) 2018-08-03 2019-08-02 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善

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US (1) US10622233B2 (enExample)
JP (1) JP7118928B2 (enExample)
KR (1) KR102558635B1 (enExample)
CN (1) CN110807273B (enExample)
TW (1) TWI790391B (enExample)

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US12276922B2 (en) 2020-05-22 2025-04-15 Tokyo Electron Limited Backside deposition tuning of stress to control wafer bow in semiconductor processing
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US12469725B2 (en) * 2021-06-27 2025-11-11 Delta Design, Inc. Method for determining corrective film pattern to reduce semiconductor wafer bow
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