TWI790391B - 基於半導體晶圓局部變形判定之全域晶圓變形的改善 - Google Patents

基於半導體晶圓局部變形判定之全域晶圓變形的改善 Download PDF

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TWI790391B
TWI790391B TW108126894A TW108126894A TWI790391B TW I790391 B TWI790391 B TW I790391B TW 108126894 A TW108126894 A TW 108126894A TW 108126894 A TW108126894 A TW 108126894A TW I790391 B TWI790391 B TW I790391B
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wafer
deformation
semiconductor wafer
backside
global
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TW108126894A
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Chinese (zh)
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TW202025235A (zh
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約書亞 豪格
那森 愛普
喬爾 埃斯特雷拉
安東 德維利耶
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日商東京威力科創股份有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
TW108126894A 2016-09-05 2019-07-30 基於半導體晶圓局部變形判定之全域晶圓變形的改善 TWI790391B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662383549P 2016-09-05 2016-09-05
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054,725 2018-08-03

Publications (2)

Publication Number Publication Date
TW202025235A TW202025235A (zh) 2020-07-01
TWI790391B true TWI790391B (zh) 2023-01-21

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US (1) US10622233B2 (enExample)
JP (1) JP7118928B2 (enExample)
KR (1) KR102558635B1 (enExample)
CN (1) CN110807273B (enExample)
TW (1) TWI790391B (enExample)

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US11393118B2 (en) * 2019-06-18 2022-07-19 Kla Corporation Metrics for asymmetric wafer shape characterization
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
KR20220167387A (ko) * 2020-05-14 2022-12-20 에이에스엠엘 네델란즈 비.브이. 제품 피쳐에 대한 분해능상 계측을 사용하는 웨이퍼 정렬 방법
US12276922B2 (en) 2020-05-22 2025-04-15 Tokyo Electron Limited Backside deposition tuning of stress to control wafer bow in semiconductor processing
US11637043B2 (en) * 2020-11-03 2023-04-25 Applied Materials, Inc. Analyzing in-plane distortion
US11829077B2 (en) 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
TW202236117A (zh) * 2021-02-03 2022-09-16 日商東京威力科創股份有限公司 膜厚分析方法、膜厚分析裝置及記錄媒體
EP4331006A4 (en) * 2021-04-27 2025-03-12 Applied Materials, Inc. Stress and overlay management for semiconductor processing
US12469725B2 (en) * 2021-06-27 2025-11-11 Delta Design, Inc. Method for determining corrective film pattern to reduce semiconductor wafer bow
US12394618B2 (en) 2021-07-08 2025-08-19 Tokyo Electron Limited Method of adjusting wafer shape using multi-directional actuation films
US12051608B2 (en) * 2021-07-20 2024-07-30 Changxin Memory Technologies, Inc. Method for adjusting wafer deformation and semiconductor structure
US11782411B2 (en) * 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
KR20230048952A (ko) * 2021-10-05 2023-04-12 삼성전자주식회사 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법
US12001147B2 (en) 2021-11-19 2024-06-04 Tokyo Electron Limited Precision multi-axis photolithography alignment correction using stressor film
EP4445218A1 (en) * 2021-12-06 2024-10-16 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
EP4202551A1 (en) * 2021-12-23 2023-06-28 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
WO2023108530A1 (en) * 2021-12-16 2023-06-22 Yangtze Memory Technologies Co., Ltd. Prediction of wafer flatness
US11994807B2 (en) 2022-05-03 2024-05-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
KR20240156433A (ko) * 2022-05-13 2024-10-29 어플라이드 머티어리얼스, 인코포레이티드 기판 곡률을 사용하여 면외 왜곡을 보상하기 위한 선량 맵핑
WO2023219983A1 (en) * 2022-05-13 2023-11-16 Applied Materials, Inc. Dose mapping and substrate rotation for substrate curvature control with improved resolution
US20240103385A1 (en) * 2022-09-28 2024-03-28 Applied Materials, Inc. Frequency and Amplitude Modulation of Implant Dose for Stress Management
US20250028294A1 (en) * 2023-07-18 2025-01-23 Applied Materials, Inc. Measurement of inherent substrate distortion
US20250216188A1 (en) * 2023-12-31 2025-07-03 Kla Corporation Calibration for in-plane distortion tool-to-tool matching
WO2025184185A1 (en) * 2024-02-28 2025-09-04 Tignis, Inc. Determination of thin film pattern to compensate substrate warpage
US20250284205A1 (en) * 2024-03-11 2025-09-11 Kla Corporation Robust and accurate overlay target design for cmp

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