KR102297701B1 - 관통-기판 비아 구조들을 갖는 본딩된 칩 어셈블리를 포함하는 3차원 메모리 디바이스 및 그 제조 방법 - Google Patents

관통-기판 비아 구조들을 갖는 본딩된 칩 어셈블리를 포함하는 3차원 메모리 디바이스 및 그 제조 방법 Download PDF

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KR102297701B1
KR102297701B1 KR1020207009288A KR20207009288A KR102297701B1 KR 102297701 B1 KR102297701 B1 KR 102297701B1 KR 1020207009288 A KR1020207009288 A KR 1020207009288A KR 20207009288 A KR20207009288 A KR 20207009288A KR 102297701 B1 KR102297701 B1 KR 102297701B1
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semiconductor
structures
substrate
bonding pad
semiconductor substrate
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KR1020207009288A
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Korean (ko)
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KR20200037444A (ko
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미츠테루 무시가
아키오 니시다
겐지 스기우라
히사카즈 오토이
마사토시 니시카와
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샌디스크 테크놀로지스 엘엘씨
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Priority claimed from US15/928,407 external-priority patent/US10354980B1/en
Priority claimed from US15/928,340 external-priority patent/US10354987B1/en
Application filed by 샌디스크 테크놀로지스 엘엘씨 filed Critical 샌디스크 테크놀로지스 엘엘씨
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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US15/928,407 2018-03-22
US15/928,340 US10354987B1 (en) 2018-03-22 2018-03-22 Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
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