EP3669398A4 - Dreidimensionale speichervorrichtung mit gebondeter chip-anordnung mit substratdurchgangsstrukturen und verfahren zur herstellung davon - Google Patents
Dreidimensionale speichervorrichtung mit gebondeter chip-anordnung mit substratdurchgangsstrukturen und verfahren zur herstellung davon Download PDFInfo
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- EP3669398A4 EP3669398A4 EP18910814.5A EP18910814A EP3669398A4 EP 3669398 A4 EP3669398 A4 EP 3669398A4 EP 18910814 A EP18910814 A EP 18910814A EP 3669398 A4 EP3669398 A4 EP 3669398A4
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
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US15/928,407 US10354980B1 (en) | 2018-03-22 | 2018-03-22 | Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same |
US15/928,340 US10354987B1 (en) | 2018-03-22 | 2018-03-22 | Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same |
PCT/US2018/062107 WO2019182657A1 (en) | 2018-03-22 | 2018-11-20 | Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same |
Publications (2)
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EP3669398A1 EP3669398A1 (de) | 2020-06-24 |
EP3669398A4 true EP3669398A4 (de) | 2021-09-01 |
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EP (1) | EP3669398A4 (de) |
KR (1) | KR102297701B1 (de) |
CN (1) | CN111247636B (de) |
WO (1) | WO2019182657A1 (de) |
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US11362108B2 (en) * | 2020-01-30 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure with a logic device and a memory device being formed in different levels, and method of forming the same |
KR102700409B1 (ko) * | 2020-02-20 | 2024-08-28 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Xtacking 아키텍처를 가진 dram 메모리 디바이스 |
CN114730772A (zh) * | 2020-03-25 | 2022-07-08 | 桑迪士克科技有限责任公司 | 接合的三维存储器器件及其通过用源极层替换承载衬底的制造方法 |
US11430950B2 (en) | 2020-03-27 | 2022-08-30 | Micron Technology, Inc. | Low resistance via contacts in a memory device |
EP4401139A2 (de) * | 2020-04-14 | 2024-07-17 | Yangtze Memory Technologies Co., Ltd. | Dreidimensionale speichervorrichtung mit rückseitigem quellkontakt |
US11699652B2 (en) | 2020-06-18 | 2023-07-11 | Micron Technology, Inc. | Microelectronic devices and electronic systems |
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US11563018B2 (en) | 2020-06-18 | 2023-01-24 | Micron Technology, Inc. | Microelectronic devices, and related methods, memory devices, and electronic systems |
US11557569B2 (en) | 2020-06-18 | 2023-01-17 | Micron Technology, Inc. | Microelectronic devices including source structures overlying stack structures, and related electronic systems |
US11705367B2 (en) | 2020-06-18 | 2023-07-18 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices, memory devices, electronic systems, and additional methods |
US11380669B2 (en) | 2020-06-18 | 2022-07-05 | Micron Technology, Inc. | Methods of forming microelectronic devices |
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CN111785726B (zh) * | 2020-07-07 | 2021-04-13 | 长江存储科技有限责任公司 | 电路芯片、三维存储器以及制备三维存储器的方法 |
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KR20220022157A (ko) * | 2020-08-18 | 2022-02-25 | 에스케이하이닉스 주식회사 | 패스 트랜지스터들을 구비하는 메모리 장치 |
CN111952318A (zh) * | 2020-08-20 | 2020-11-17 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
US11825658B2 (en) | 2020-08-24 | 2023-11-21 | Micron Technology, Inc. | Methods of forming microelectronic devices and memory devices |
US11417676B2 (en) * | 2020-08-24 | 2022-08-16 | Micron Technology, Inc. | Methods of forming microelectronic devices and memory devices, and related microelectronic devices, memory devices, and electronic systems |
US11963352B2 (en) | 2020-08-31 | 2024-04-16 | Sandisk Technologies Llc | Three-dimensional memory device with vertical field effect transistors and method of making thereof |
WO2022046239A1 (en) * | 2020-08-31 | 2022-03-03 | Sandisk Technologies Llc | Three-dimensional memory device with vertical field effect transistors and method of making thereof |
US11296113B2 (en) | 2020-08-31 | 2022-04-05 | Sandisk Technologies Llc | Three-dimensional memory device with vertical field effect transistors and method of making thereof |
US11569215B2 (en) | 2020-08-31 | 2023-01-31 | Sandisk Technologies Llc | Three-dimensional memory device with vertical field effect transistors and method of making thereof |
CN112204734B (zh) * | 2020-09-02 | 2024-09-17 | 长江存储科技有限责任公司 | 半导体器件的焊盘结构 |
JP2022050956A (ja) * | 2020-09-18 | 2022-03-31 | キオクシア株式会社 | 半導体記憶装置 |
CN112289797A (zh) * | 2020-10-28 | 2021-01-29 | 长江存储科技有限责任公司 | 一种外围电路及三维存储器 |
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2018
- 2018-11-20 EP EP18910814.5A patent/EP3669398A4/de active Pending
- 2018-11-20 CN CN201880068190.7A patent/CN111247636B/zh active Active
- 2018-11-20 WO PCT/US2018/062107 patent/WO2019182657A1/en unknown
- 2018-11-20 KR KR1020207009288A patent/KR102297701B1/ko active IP Right Grant
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Also Published As
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KR102297701B1 (ko) | 2021-09-06 |
WO2019182657A1 (en) | 2019-09-26 |
CN111247636B (zh) | 2024-04-19 |
KR20200037444A (ko) | 2020-04-08 |
EP3669398A1 (de) | 2020-06-24 |
CN111247636A (zh) | 2020-06-05 |
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