KR102241181B1 - 핀 기반 일렉트로닉스를 위한 고체 소스 확산 접합 - Google Patents

핀 기반 일렉트로닉스를 위한 고체 소스 확산 접합 Download PDF

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KR102241181B1
KR102241181B1 KR1020167034750A KR20167034750A KR102241181B1 KR 102241181 B1 KR102241181 B1 KR 102241181B1 KR 1020167034750 A KR1020167034750 A KR 1020167034750A KR 20167034750 A KR20167034750 A KR 20167034750A KR 102241181 B1 KR102241181 B1 KR 102241181B1
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South Korea
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fin
end portion
layer
integrated circuit
circuit structure
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Korean (ko)
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KR20170028882A (ko
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왈리드 엠. 하페즈
치아-홍 잔
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인텔 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
    • H01L29/66901—
    • H01L29/0657—
    • H01L29/66166—
    • H01L29/7855—
    • H01L29/808—
    • H01L29/8605—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/025—Manufacture or treatment of resistors having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/43—Resistors having PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0241—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] doping of vertical sidewalls, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6215—Fin field-effect transistors [FinFET] having multiple independently-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/87—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of PN-junction gate FETs

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Element Separation (AREA)
KR1020167034750A 2014-07-14 2014-07-14 핀 기반 일렉트로닉스를 위한 고체 소스 확산 접합 Active KR102241181B1 (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/046525 WO2016010515A1 (en) 2014-07-14 2014-07-14 Solid-source diffused junction for fin-based electronics

Publications (2)

Publication Number Publication Date
KR20170028882A KR20170028882A (ko) 2017-03-14
KR102241181B1 true KR102241181B1 (ko) 2021-04-16

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KR1020167034750A Active KR102241181B1 (ko) 2014-07-14 2014-07-14 핀 기반 일렉트로닉스를 위한 고체 소스 확산 접합

Country Status (7)

Country Link
US (6) US9842944B2 (https=)
EP (2) EP3170207A4 (https=)
JP (1) JP6399464B2 (https=)
KR (1) KR102241181B1 (https=)
CN (2) CN112670349B (https=)
TW (3) TWI628801B (https=)
WO (1) WO2016010515A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842944B2 (en) 2014-07-14 2017-12-12 Intel Corporation Solid-source diffused junction for fin-based electronics
US10304681B2 (en) * 2015-06-22 2019-05-28 Intel Corporation Dual height glass for finFET doping
US9847388B2 (en) * 2015-09-01 2017-12-19 International Business Machines Corporation High thermal budget compatible punch through stop integration using doped glass
US9976650B1 (en) * 2017-02-01 2018-05-22 Deere & Company Forkless synchronizer with sensor rail arrangement
EP3545556A4 (en) * 2017-03-30 2020-10-14 INTEL Corporation VERTICALLY STACKED TRANSISTORS IN A FIN
US10401122B2 (en) 2017-06-08 2019-09-03 Springfield, Inc. Free floating handguard anchoring system
US20190172920A1 (en) * 2017-12-06 2019-06-06 Nanya Technology Corporation Junctionless transistor device and method for preparing the same
WO2019132876A1 (en) * 2017-12-27 2019-07-04 Intel Corporation Finfet based capacitors and resistors and related apparatuses, systems, and methods
US10325819B1 (en) * 2018-03-13 2019-06-18 Globalfoundries Inc. Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device
KR102813445B1 (ko) * 2019-10-02 2025-05-27 삼성전자주식회사 집적회로 소자 및 그 제조 방법
CN113921520B (zh) * 2021-09-29 2024-08-06 上海晶丰明源半导体股份有限公司 射频开关器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2011040768A (ja) * 2005-08-19 2011-02-24 Infineon Technologies Ag 電気回路中にて静電気放電保護素子として用いるためのゲート制御されたフィン型抵抗素子、および、電気回路内部を静電気放電から保護するための保護装置
US20130043536A1 (en) * 2011-08-19 2013-02-21 Irfan Rahim Buffered finfet device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
US7235436B1 (en) * 2003-07-08 2007-06-26 Advanced Micro Devices, Inc. Method for doping structures in FinFET devices
JP2005174964A (ja) * 2003-12-05 2005-06-30 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP4504214B2 (ja) * 2005-02-04 2010-07-14 株式会社東芝 Ｍｏｓ型半導体装置及びその製造方法
US7402856B2 (en) * 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US7560784B2 (en) * 2007-02-01 2009-07-14 International Business Machines Corporation Fin PIN diode
US8130547B2 (en) 2007-11-29 2012-03-06 Zeno Semiconductor, Inc. Method of maintaining the state of semiconductor memory having electrically floating body transistor
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8030144B2 (en) * 2009-10-09 2011-10-04 Globalfoundries Inc. Semiconductor device with stressed fin sections, and related fabrication methods
US8592918B2 (en) * 2009-10-28 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Forming inter-device STI regions and intra-device STI regions using different dielectric materials
US8158500B2 (en) * 2010-01-27 2012-04-17 International Business Machines Corporation Field effect transistors (FETS) and methods of manufacture
US8889494B2 (en) * 2010-12-29 2014-11-18 Globalfoundries Singapore Pte. Ltd. Finfet
US8435845B2 (en) * 2011-04-06 2013-05-07 International Business Machines Corporation Junction field effect transistor with an epitaxially grown gate structure
US9082853B2 (en) * 2012-10-31 2015-07-14 International Business Machines Corporation Bulk finFET with punchthrough stopper region and method of fabrication
US9299840B2 (en) * 2013-03-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9431497B2 (en) * 2013-05-21 2016-08-30 Globalfoundries Singapore Pte. Ltd. Transistor devices having an anti-fuse configuration and methods of forming the same
CN104218082B (zh) * 2013-06-04 2017-08-25 中芯国际集成电路制造(上海)有限公司 高迁移率鳍型场效应晶体管及其制造方法
US9293534B2 (en) * 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
CN104576383B (zh) * 2013-10-14 2017-09-12 中国科学院微电子研究所 一种FinFET结构及其制造方法
US9842944B2 (en) * 2014-07-14 2017-12-12 Intel Corporation Solid-source diffused junction for fin-based electronics

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2011040768A (ja) * 2005-08-19 2011-02-24 Infineon Technologies Ag 電気回路中にて静電気放電保護素子として用いるためのゲート制御されたフィン型抵抗素子、および、電気回路内部を静電気放電から保護するための保護装置
US20130043536A1 (en) * 2011-08-19 2013-02-21 Irfan Rahim Buffered finfet device

Also Published As

Publication number Publication date
EP3300119A1 (en) 2018-03-28
EP3170207A1 (en) 2017-05-24
EP3170207A4 (en) 2018-03-28
CN112670349A (zh) 2021-04-16
TWI628801B (zh) 2018-07-01
JP6399464B2 (ja) 2018-10-03
US20180158906A1 (en) 2018-06-07
US20200335582A1 (en) 2020-10-22
US20190296105A1 (en) 2019-09-26
US20220102488A1 (en) 2022-03-31
CN106471624A (zh) 2017-03-01
US11139370B2 (en) 2021-10-05
US10355081B2 (en) 2019-07-16
TW201828482A (zh) 2018-08-01
TWI600166B (zh) 2017-09-21
JP2017527099A (ja) 2017-09-14
TW201727926A (zh) 2017-08-01
US20170133461A1 (en) 2017-05-11
US20170018658A1 (en) 2017-01-19
TW201614852A (en) 2016-04-16
CN112670349B (zh) 2024-09-17
WO2016010515A1 (en) 2016-01-21
TWI664738B (zh) 2019-07-01
US9899472B2 (en) 2018-02-20
US10741640B2 (en) 2020-08-11
KR20170028882A (ko) 2017-03-14
US11764260B2 (en) 2023-09-19
US9842944B2 (en) 2017-12-12
CN106471624B (zh) 2021-01-05

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