KR102035258B1 - 구획된 다중-홉 네트워크를 갖는 다이-스택된 디바이스 - Google Patents

구획된 다중-홉 네트워크를 갖는 다이-스택된 디바이스 Download PDF

Info

Publication number
KR102035258B1
KR102035258B1 KR1020157016648A KR20157016648A KR102035258B1 KR 102035258 B1 KR102035258 B1 KR 102035258B1 KR 1020157016648 A KR1020157016648 A KR 1020157016648A KR 20157016648 A KR20157016648 A KR 20157016648A KR 102035258 B1 KR102035258 B1 KR 102035258B1
Authority
KR
South Korea
Prior art keywords
die
link
routing
dies
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020157016648A
Other languages
English (en)
Korean (ko)
Other versions
KR20150099759A (ko
Inventor
미수나 에스. 소테소디
가브리엘 에이치. 로우
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20150099759A publication Critical patent/KR20150099759A/ko
Application granted granted Critical
Publication of KR102035258B1 publication Critical patent/KR102035258B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H01L25/0652—
    • G06F17/5068—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H01L23/481—
    • H01L23/5384—
    • H01L23/5389—
    • H01L25/18—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/02—Topology update or discovery
    • H04L45/021—Ensuring consistency of routing table updates, e.g. by using epoch numbers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020157016648A 2012-12-23 2013-12-18 구획된 다중-홉 네트워크를 갖는 다이-스택된 디바이스 Active KR102035258B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/726,142 2012-12-23
US13/726,142 US9065722B2 (en) 2012-12-23 2012-12-23 Die-stacked device with partitioned multi-hop network
PCT/US2013/075956 WO2014100090A1 (en) 2012-12-23 2013-12-18 Die-stacked device with partitioned multi-hop network

Publications (2)

Publication Number Publication Date
KR20150099759A KR20150099759A (ko) 2015-09-01
KR102035258B1 true KR102035258B1 (ko) 2019-10-22

Family

ID=50974600

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157016648A Active KR102035258B1 (ko) 2012-12-23 2013-12-18 구획된 다중-홉 네트워크를 갖는 다이-스택된 디바이스

Country Status (6)

Country Link
US (2) US9065722B2 (https=)
EP (1) EP2936554B1 (https=)
JP (1) JP6101821B2 (https=)
KR (1) KR102035258B1 (https=)
CN (1) CN104885212B (https=)
WO (1) WO2014100090A1 (https=)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9065722B2 (en) 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US9354990B2 (en) 2013-09-11 2016-05-31 International Business Machines Corporation Coordination of spare lane usage between link partners
EP3087491B1 (en) * 2013-12-26 2018-12-05 Intel Corporation Multichip package link
US9558143B2 (en) * 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
US9330433B2 (en) * 2014-06-30 2016-05-03 Intel Corporation Data distribution fabric in scalable GPUs
JP6313140B2 (ja) * 2014-06-30 2018-04-18 株式会社東芝 通信装置及びマルチホッピングネットワーク
US9287208B1 (en) 2014-10-27 2016-03-15 Intel Corporation Architecture for on-die interconnect
US9236328B1 (en) * 2014-10-27 2016-01-12 International Business Machines Corporation Electrical and optical through-silicon-via (TSV)
JP6362524B2 (ja) * 2014-11-28 2018-07-25 イビデン株式会社 半導体装置及びその製造方法
US9971733B1 (en) 2014-12-04 2018-05-15 Altera Corporation Scalable 2.5D interface circuitry
US9666562B2 (en) 2015-01-15 2017-05-30 Qualcomm Incorporated 3D integrated circuit
US10116557B2 (en) * 2015-05-22 2018-10-30 Gray Research LLC Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits and applications of the router and network
US9693124B2 (en) * 2015-06-09 2017-06-27 Oracle International Corporation Macro-switch with a buffered switching matrix
US9761533B2 (en) 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect
KR102379704B1 (ko) * 2015-10-30 2022-03-28 삼성전자주식회사 반도체 패키지
US20170153892A1 (en) * 2015-11-30 2017-06-01 Intel Corporation Instruction And Logic For Programmable Fabric Hierarchy And Cache
US9837391B2 (en) * 2015-12-11 2017-12-05 Intel Corporation Scalable polylithic on-package integratable apparatus and method
US9946674B2 (en) * 2016-04-28 2018-04-17 Infineon Technologies Ag Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller
US10304802B2 (en) 2016-05-02 2019-05-28 International Business Machines Corporation Integrated wafer-level processing system
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
WO2018034787A1 (en) * 2016-08-15 2018-02-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (ssi) technology integration
US10784121B2 (en) * 2016-08-15 2020-09-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (SSI) technology integration
US10068879B2 (en) 2016-09-19 2018-09-04 General Electric Company Three-dimensional stacked integrated circuit devices and methods of assembling the same
US10672745B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D processor
CN119028958A (zh) 2016-10-07 2024-11-26 艾克瑟尔西斯公司 直接键合原生互连件和有源基部管芯
US10580757B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Face-to-face mounted IC dies with orthogonal top interconnect layers
EP4089531B1 (en) 2016-12-31 2024-06-26 Intel Corporation Systems, methods, and apparatuses for heterogeneous computing
US10587534B2 (en) 2017-04-04 2020-03-10 Gray Research LLC Composing cores and FPGAS at massive scale with directional, two dimensional routers and interconnection networks
US10496561B2 (en) * 2017-04-18 2019-12-03 Advanced Micro Devices, Inc. Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies
US11604754B2 (en) * 2017-05-25 2023-03-14 Advanced Micro Devices, Inc. Method and apparatus of integrating memory stacks
KR102395446B1 (ko) * 2017-09-28 2022-05-10 삼성전자주식회사 적층형 반도체 장치, 이를 포함하는 시스템 및 적층형 반도체 장치에서의 신호 전송 방법
US10936221B2 (en) 2017-10-24 2021-03-02 Micron Technology, Inc. Reconfigurable memory architectures
US11281608B2 (en) 2017-12-11 2022-03-22 Micron Technology, Inc. Translation system for finer grain memory architectures
US10534545B2 (en) * 2017-12-20 2020-01-14 International Business Machines Corporation Three-dimensional stacked memory optimizations for latency and power
CN111758156A (zh) * 2017-12-22 2020-10-09 德克萨斯大学系统董事会 纳米级对准的三维堆叠式集成电路
US11569173B2 (en) * 2017-12-29 2023-01-31 Intel Corporation Bridge hub tiling architecture
US10685947B2 (en) 2018-01-12 2020-06-16 Intel Corporation Distributed semiconductor die and package architecture
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US10505548B1 (en) * 2018-05-25 2019-12-10 Xilinx, Inc. Multi-chip structure having configurable network-on-chip
US12300688B2 (en) * 2018-07-02 2025-05-13 Shanghai Denglin Technologies Co. Ltd Configurable random-access memory (RAM) array including through-silicon via (TSV) bypassing physical layer
US11222884B2 (en) 2018-11-28 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Layout design methodology for stacked devices
US10666264B1 (en) 2018-12-13 2020-05-26 Micron Technology, Inc. 3D stacked integrated circuits having failure management
US11672111B2 (en) 2018-12-26 2023-06-06 Ap Memory Technology Corporation Semiconductor structure and method for manufacturing a plurality thereof
US11417628B2 (en) 2018-12-26 2022-08-16 Ap Memory Technology Corporation Method for manufacturing semiconductor structure
US11476241B2 (en) * 2019-03-19 2022-10-18 Micron Technology, Inc. Interposer, microelectronic device assembly including same and methods of fabrication
US11036660B2 (en) * 2019-03-28 2021-06-15 Intel Corporation Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices
US11282824B2 (en) 2019-04-23 2022-03-22 Xilinx, Inc. Multi-chip structure including a memory die stacked on die having programmable integrated circuit
CN115567451A (zh) * 2019-06-04 2023-01-03 华为技术有限公司 一种转发报文的方法、装置和网络设备
US11264361B2 (en) * 2019-06-05 2022-03-01 Invensas Corporation Network on layer enabled architectures
US10879903B2 (en) * 2019-06-28 2020-12-29 Intel Corporation Distributed I/O interfaces in modularized integrated circuit devices
US11841803B2 (en) 2019-06-28 2023-12-12 Advanced Micro Devices, Inc. GPU chiplets using high bandwidth crosslinks
US10991635B2 (en) * 2019-07-20 2021-04-27 International Business Machines Corporation Multiple chip bridge connector
US11804479B2 (en) 2019-09-27 2023-10-31 Advanced Micro Devices, Inc. Scheme for enabling die reuse in 3D stacked products
WO2021072670A1 (zh) * 2019-10-16 2021-04-22 华为技术有限公司 芯片和集成芯片
WO2021168837A1 (zh) * 2020-02-28 2021-09-02 华为技术有限公司 一种数据处理装置及方法
CN113629048B (zh) * 2020-05-07 2024-12-10 爱普科技股份有限公司 半导体结构及制造多个半导体结构的方法
KR102766659B1 (ko) 2020-05-20 2025-02-12 에스케이하이닉스 주식회사 코어 다이가 제어 다이에 스택된 스택 패키지
CN111725188B (zh) * 2020-07-01 2021-12-07 无锡中微亿芯有限公司 一种硅连接层具有可配置电路的多裸片fpga
US11609846B2 (en) * 2020-09-11 2023-03-21 Micron Technology, Inc. Managing workload of programming sets of pages to memory device
JP7164267B2 (ja) * 2020-12-07 2022-11-01 インテル・コーポレーション ヘテロジニアスコンピューティングのためのシステム、方法及び装置
US11769731B2 (en) * 2021-01-14 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd Architecture for computing system package
CN115514704B (zh) * 2022-07-18 2023-08-22 华为技术有限公司 一种通信芯片及数据交换装置、交换设备
US12543597B2 (en) 2022-07-25 2026-02-03 Avago Technologies International Sales Pte. Limited Partitioned overlapped copper-bonded interposers
US12450182B2 (en) * 2022-11-14 2025-10-21 Faisal A. Qureshi Distributed queue multi-bus on multi-CPU chips
US20240387388A1 (en) * 2023-05-18 2024-11-21 Xilinx, Inc. Memory bandwidth through vertical connections
WO2024262220A1 (ja) * 2023-06-20 2024-12-26 先端システム技術研究組合 半導体モジュール
JPWO2024262221A1 (https=) * 2023-06-20 2024-12-26
US20230342309A1 (en) * 2023-06-30 2023-10-26 Intel Corporation Circuit Systems And Methods For Transmitting Signals Between Devices
US12506696B2 (en) * 2023-08-09 2025-12-23 Achronix Semiconductor Corporation Sliced router for network on a chip
TWI902072B (zh) 2023-11-28 2025-10-21 財團法人工業技術研究院 半導體裝置及半導體裝置間的通訊方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090210600A1 (en) 2008-02-19 2009-08-20 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
US20120147567A1 (en) 2010-12-09 2012-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Networking Packages Based on Interposers
US20120204073A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Ieee 1149.1 interposer method and apparatus
US20120273782A1 (en) 2011-04-28 2012-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interposers of 3-dimensional integrated circuit package systems and methods of designing the same
US20120319717A1 (en) 2011-06-16 2012-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for 3d ic test

Family Cites Families (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391917A (en) * 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US6189065B1 (en) 1998-09-28 2001-02-13 International Business Machines Corporation Method and apparatus for interrupt load balancing for powerPC processors
US6519674B1 (en) 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US7308524B2 (en) 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US20040153902A1 (en) 2003-01-21 2004-08-05 Nexflash Technologies, Inc. Serial flash integrated circuit having error detection and correction
KR100601881B1 (ko) * 2004-01-28 2006-07-19 삼성전자주식회사 원칩 시스템에서 라우터들간의 라우팅 경로 설정 장치 및방법
TWI242855B (en) 2004-10-13 2005-11-01 Advanced Semiconductor Eng Chip package structure, package substrate and manufacturing method thereof
US7327600B2 (en) 2004-12-23 2008-02-05 Unity Semiconductor Corporation Storage controller for multiple configurations of vertical memory
US7477535B2 (en) 2006-10-05 2009-01-13 Nokia Corporation 3D chip arrangement including memory manager
GB0620043D0 (en) 2006-10-10 2006-11-22 Univ Belfast Improvements relating to the detection of malicious content in date
WO2008076790A2 (en) 2006-12-14 2008-06-26 Rambus Inc. Multi-die memory device
US8423789B1 (en) 2007-05-22 2013-04-16 Marvell International Ltd. Key generation techniques
US7849383B2 (en) 2007-06-25 2010-12-07 Sandisk Corporation Systems and methods for reading nonvolatile memory using multiple reading schemes
US8338267B2 (en) 2007-07-11 2012-12-25 Sematech, Inc. Systems and methods for vertically integrating semiconductor devices
US8356138B1 (en) 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US8156307B2 (en) 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US7623365B2 (en) * 2007-08-29 2009-11-24 Micron Technology, Inc. Memory device interface methods, apparatus, and systems
JP4775969B2 (ja) 2007-09-03 2011-09-21 ルネサスエレクトロニクス株式会社 不揮発性記憶装置
US8064739B2 (en) 2007-10-23 2011-11-22 Hewlett-Packard Development Company, L.P. Three-dimensional die stacks with inter-device and intra-device optical interconnect
US8059443B2 (en) 2007-10-23 2011-11-15 Hewlett-Packard Development Company, L.P. Three-dimensional memory module architectures
US8169808B2 (en) 2008-01-25 2012-05-01 Micron Technology, Inc. NAND flash content addressable memory
US8397084B2 (en) 2008-06-12 2013-03-12 Microsoft Corporation Single instance storage of encrypted data
JP2010021306A (ja) 2008-07-10 2010-01-28 Hitachi Ltd 半導体装置
US7930661B1 (en) 2008-08-04 2011-04-19 Xilinx, Inc. Software model for a hybrid stacked field programmable gate array
US7872936B2 (en) 2008-09-17 2011-01-18 Qimonda Ag System and method for packaged memory
US8037354B2 (en) 2008-09-18 2011-10-11 Honeywell International Inc. Apparatus and method for operating a computing platform without a battery pack
US7796446B2 (en) 2008-09-19 2010-09-14 Qimonda Ag Memory dies for flexible use and method for configuring memory dies
US20100162065A1 (en) 2008-12-19 2010-06-24 Unity Semiconductor Corporation Protecting integrity of data in multi-layered memory with data redundancy
US20100157644A1 (en) 2008-12-19 2010-06-24 Unity Semiconductor Corporation Configurable memory interface to provide serial and parallel access to memories
US20100167100A1 (en) 2008-12-26 2010-07-01 David Roger Moore Composite membrane and method for making
US8032804B2 (en) 2009-01-12 2011-10-04 Micron Technology, Inc. Systems and methods for monitoring a memory system
US8127185B2 (en) * 2009-01-23 2012-02-28 Micron Technology, Inc. Memory devices and methods for managing error regions
US8977805B2 (en) 2009-03-25 2015-03-10 Apple Inc. Host-assisted compaction of memory blocks
US8451014B2 (en) 2009-09-09 2013-05-28 Advanced Micro Devices, Inc. Die stacking, testing and packaging for yield
US8492905B2 (en) * 2009-10-07 2013-07-23 Qualcomm Incorporated Vertically stackable dies having chip identifier structures
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
JP2013522779A (ja) 2010-03-22 2013-06-13 モサイド・テクノロジーズ・インコーポレーテッド 誤り訂正を有する複合半導体メモリデバイス
US8519739B1 (en) 2010-05-03 2013-08-27 ISC8 Inc. High-speed processor core comprising direct processor-to-memory connectivity
KR20140001192A (ko) 2010-06-25 2014-01-06 심볼릭 로직 리미티드 메모리 디바이스
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8407245B2 (en) 2010-11-24 2013-03-26 Microsoft Corporation Efficient string pattern matching for large pattern sets
US8700951B1 (en) 2011-03-09 2014-04-15 Western Digital Technologies, Inc. System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata
US20120290793A1 (en) 2011-05-10 2012-11-15 Jaewoong Chung Efficient tag storage for large data caches
GB2493195A (en) * 2011-07-28 2013-01-30 St Microelectronics Res & Dev Address translation and routing between dies in a system in package.
JP5524144B2 (ja) 2011-08-08 2014-06-18 株式会社東芝 ｋｅｙ−ｖａｌｕｅストア方式を有するメモリシステム
US8793467B2 (en) 2011-09-30 2014-07-29 Pure Storage, Inc. Variable length encoding in a storage system
JP5694101B2 (ja) 2011-09-20 2015-04-01 株式会社東芝 メモリ・デバイス、ホスト・デバイス
US20130073755A1 (en) 2011-09-20 2013-03-21 Advanced Micro Devices, Inc. Device protocol translator for connection of external devices to a processing unit package
US9100348B2 (en) * 2011-10-03 2015-08-04 Intel Corporation Managing sideband routers in on-die system fabric
JP5970078B2 (ja) 2011-12-02 2016-08-17 インテル・コーポレーション デバイス相互接続の変化を可能にする積層メモリ
KR20130071884A (ko) * 2011-12-21 2013-07-01 삼성전자주식회사 다이 패키지 및 이를 포함하는 시스템
US8778734B2 (en) * 2012-03-28 2014-07-15 Advanced Micro Devices, Inc. Tree based adaptive die enumeration
CN104205234B (zh) 2012-03-30 2017-07-11 英特尔公司 用于存储器电路测试引擎的通用数据加扰器
US9030253B1 (en) * 2012-05-30 2015-05-12 Altera Corporation Integrated circuit package with distributed clock network
US8922243B2 (en) 2012-12-23 2014-12-30 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20140040532A1 (en) 2012-08-06 2014-02-06 Advanced Micro Devices, Inc. Stacked memory device with helper processor
US9697147B2 (en) 2012-08-06 2017-07-04 Advanced Micro Devices, Inc. Stacked memory device with metadata management
US8546955B1 (en) * 2012-08-16 2013-10-01 Xilinx, Inc. Multi-die stack package
US8737108B2 (en) 2012-09-25 2014-05-27 Intel Corporation 3D memory configurable for performance and power
US9515899B2 (en) 2012-12-19 2016-12-06 Veritas Technologies Llc Providing optimized quality of service to prioritized virtual machines and applications based on quality of shared resources
US9201777B2 (en) 2012-12-23 2015-12-01 Advanced Micro Devices, Inc. Quality of service support using stacked memory device with logic die
US9170948B2 (en) 2012-12-23 2015-10-27 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die
US9065722B2 (en) 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
US9286948B2 (en) 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090210600A1 (en) 2008-02-19 2009-08-20 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
US20120147567A1 (en) 2010-12-09 2012-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Networking Packages Based on Interposers
US20120204073A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Ieee 1149.1 interposer method and apparatus
US20120273782A1 (en) 2011-04-28 2012-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interposers of 3-dimensional integrated circuit package systems and methods of designing the same
US20120319717A1 (en) 2011-06-16 2012-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for 3d ic test

Also Published As

Publication number Publication date
WO2014100090A1 (en) 2014-06-26
CN104885212A (zh) 2015-09-02
JP6101821B2 (ja) 2017-03-22
US9065722B2 (en) 2015-06-23
JP2016502287A (ja) 2016-01-21
CN104885212B (zh) 2017-05-03
US20140177626A1 (en) 2014-06-26
KR20150099759A (ko) 2015-09-01
EP2936554A1 (en) 2015-10-28
US20150357306A1 (en) 2015-12-10
EP2936554A4 (en) 2016-08-31
EP2936554B1 (en) 2021-03-17
US9825843B2 (en) 2017-11-21

Similar Documents

Publication Publication Date Title
KR102035258B1 (ko) 구획된 다중-홉 네트워크를 갖는 다이-스택된 디바이스
US12321597B2 (en) Method and apparatus to enable individual non volatile memory express (NVME) input/output (IO) queues on differing network addresses of an NVME controller
US9432298B1 (en) System, method, and computer program product for improving memory systems
JP5784582B2 (ja) コンフィギュラブルな帯域幅メモリ・デバイスおよび方法
US9135185B2 (en) Die-stacked memory device providing data translation
CN104541257B (zh) 利用元数据管理的堆栈存储器设备
US9286948B2 (en) Query operations for stacked-die memory device
CN111261204B (zh) 存储系统
WO2024221975A1 (zh) 融合架构系统、非易失性存储系统及存储资源获取方法
CN104202197A (zh) 设备管理的方法和装置
CN109314103B (zh) 用于远程现场可编程门阵列处理的方法和装置
CN104598405A (zh) 扩展芯片及可扩展的芯片系统及控制方法
CN116303155A (zh) 异构存储器目标的交错
CN102622191B (zh) 一种高速海量存储板
CN102752207A (zh) 可重配置的2D mesh片上网络结构及其重配置方法
CN116964569A (zh) 相邻处理器的光桥互连单元
CN204347812U (zh) 一种基于fpga的服务器存储电路
KR102850132B1 (ko) 상보적 다이-대-다이 인터페이스
CN205050007U (zh) 一种基于融合架构在刀片式服务器中的存储扩展卡
US20240273040A1 (en) Multi-Stack Compute Chip and Memory Architecture
CN204496487U (zh) 扩展芯片及可扩展的芯片系统
CN203164946U (zh) 一种用于服务器的多盘存储装置
CN120631815A (zh) 基于3d-dram的外部存储方案

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 7

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000