CN111758156A - 纳米级对准的三维堆叠式集成电路 - Google Patents

纳米级对准的三维堆叠式集成电路 Download PDF

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Publication number
CN111758156A
CN111758156A CN201880090163.XA CN201880090163A CN111758156A CN 111758156 A CN111758156 A CN 111758156A CN 201880090163 A CN201880090163 A CN 201880090163A CN 111758156 A CN111758156 A CN 111758156A
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die
layer
wafer
dimensional
nanometer
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希德加塔·V·斯林瓦森
帕拉斯·阿杰伊
阿西姆·赛亚尔
奥瓦迪亚·阿贝
马克·麦克德莫特
杰迪普·库尔卡尼
希拉旺·辛格尔
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University of Texas System
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University of Texas System
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Abstract

一种用于制造三维(3D)堆叠式集成电路的方法。利用取放策略将源晶圆与利用标准二维(2D)半导体制造技术制造的器件层堆叠在一起。源晶圆可以以顺序或平行的方式堆叠。该堆叠可以以面对面、面对背、背对面或背对背的方式进行。可使用硅通孔(TSV)来连接以面对面、背对面或背对背的方式堆叠的源晶圆。或者，可使用层间通孔(ILV)来连接以面对面方式堆叠的源晶圆。

Description

纳米级对准的三维堆叠式集成电路
相关申请的交叉引用
本申请要求于2017年12月22日提交的标题为“纳米级对准的3D堆叠式集成电路”的美国临时专利申请序列号62/609,891的优先权，其全部内容通过引用并入本文。
技术领域
本发明大体上涉及半导体制造，并且更具体地涉及纳米级对准的三维(3D)堆叠式集成电路。
背景技术
摩尔定律表明，密集集成电路中的晶体管数量大约每两年翻一番。随着特征件尺寸已达到原子尺度，目前，以摩尔定律为特征的电子电路的二维(2D)缩放可能在近期达到极限。例如，用于10纳米技术节点的高K覆盖层(capping layer)的厚度接近0.5纳米，其小于两个硅原子的宽度。多图案化技术(multi-patterning technology，MPT)的计量精度要求接近0.2纳米，其小于一个硅原子的宽度。
鉴于这些和其他的限制，2D缩放和通常的自上而下制造方式对于7纳米节点及超越7纳米节点的继续发展来说存在重大挑战。
发明内容
在本发明的一个实施方案中，一种用于制造三维(3D)片上系统(system on chip，SoC)的方法包括：将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，第(k-1)层晶圆填充有2D管芯，k是大于1的正整数。2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛。该方法还包括：布置允许第k层2D管芯阵列与第(k-1)层2D管芯阵列之间进行经润滑的相对运动的流体，其中，该流体允许第k层和第(k-1)层2D管芯阵列之间的精确套刻。
在本发明的另一实施方案中，一种用于制造三维(3D)片上系统(SoC)的方法包括：将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，第(k-1)层晶圆填充有2D管芯，其中，k是大于1的正整数。2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛。该方法还包括：提供封装层，用于保护在第k层晶圆和第(k-1)层晶圆中的每一层中的2D管芯免受在取放(pick-and-place)过程中所使用的蚀刻剂的影响。
在本发明的另一实施方案中，一种用于制造三维(3D)片上系统(SoC)的方法包括：将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，第(k-1)层晶圆填充有2D管芯，其中，k是大于1的正整数。此外，2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛。另外，2D管芯的厚度小于10微米。
在本发明的另一个实施方案中，一种用于设计三维(3D)专用集成电路(Application-Specific Integrated Circuit，ASIC)片上系统(SoC)逻辑电路的电子设计自动化(electronic design automation，EDA)方法包括：集成有二维(2D)EDA解决方案的软件的组合，其中，所述软件包括网表划分算法，以将3D设计网表划分为2D模块。2D EDA解决方案用于执行以下一项或多项：合成(synthesis)、3D布局感知合成(3D placementaware synthesis)、布局(placement)、时钟树合成(clock tree synthesis，CTS)、布线(routing)、设计验证(design verification)和签核分析(signoff analysis)。
前述内容相当概括地概述了本发明的一个或多个实施方案的特征和技术优点，以便可以更好地理解以下对本发明的详细描述。在下文中将描述本发明的附加特征和优点，其可以形成本发明的权利要求的主题。
附图说明
当结合以下附图考虑以下详细描述时，可以更好地理解本发明，其中：
图1示出了根据本发明的实施方案的示例性第k层源晶圆，其示出了多种2D管芯排列；
图2示出了根据本发明的实施方案的将第k层2D管芯阵列(k＞1)堆叠到第1层2D管芯阵列上；
图3A至3B示出了根据本发明的实施方案的具有两个掩埋层的第k层绝缘体上硅(Silicon-On-Insulator，SOI)晶圆的横截面；
图4A至4B示出了根据本发明的实施方案的第k层SOI晶圆的另一横截面；
图5A至5B示出了根据本发明的实施方案的第k层SOI晶圆的又一横截面；
图6是根据本发明的实施方案的基于背面研磨方式的翻转和散装物料去除方法的流程图；
图7A至7D描绘了根据本发明的实施方案的使用图6中描述的步骤进行的翻转和散装物料去除的剖视图；
图8是根据本发明的实施方案的基于剥离方式的翻转和散装物料去除方法的流程图；
图9A至9E描绘了根据本发明的实施方案的使用图8中描述的步骤进行的翻转和散装物料去除的剖视图；
图10是根据本发明的实施方案的用于多个经封装的2D管芯的套刻和变形控制的方法的流程图；
图11A至图11B描绘了根据本发明的实施方案的使用图10中描述的步骤来提供多个经封装的2D管芯的套刻和变形控制的剖视图；
图12A至图12B示出了根据本发明的实施方案的单拾取的2D管芯的套刻和变形控制；
图13示出了根据本发明的实施方案的通过已经存在于经取放的2D管芯中的通导孔制成穿硅通孔(Through Silicon Vias，TSV)；
图14A至14C示出了根据本发明的实施方案的用于临时附接和绑定(bonding)的示例性过程；
图15示出了根据本发明的实施方案的用于逻辑实现的常规2D专用集成电路(ASIC)电子设计自动化(EDA)流程；
图16示出了根据本发明的实施方案的2D单面静态随机存取存储器(staticrandom access memory，SRAM)配置；
图17示出了根据本发明的实施方案的3D独立SRAM管芯堆叠；
图18示出了根据本发明的实施方案的3D仅位单元堆叠的SRAM；以及
图19示出了根据本发明的实施方案的用于3D仅位单元堆叠的SRAM的垂直位线横截面。
具体实施方式
如背景技术部分所述，二维(2D)缩放和通常的自上而下制造方式对于7纳米节点及超过7纳米节点的继续发展来说存在重大挑战。
如下文所讨论的，本发明的实施方案通过在第三(3rd)维度上进行缩放来应对这样的挑战。
在一个实施方案中，本发明使用具有利用标准2D半导体制造工艺(下文结合图1进行讨论)制造的器件层的源晶圆，并利用取放策略将它们(源晶圆)以顺序或平行方式进行堆叠。Sreenivasan等人在文献WO 2018/119451A1(下文中称为“Sreenivasan等人”)中讨论了这样的取放策略，该文献通过引用整体并入本文。在一个实施方案中，堆叠以面对面(face-to-face，F2F)、面对背(face-to-back，F2B)、背对面(back-to-face，B2F)或背对背(back-to-back，B2B)的方式发生。例如，可使用穿硅通孔(TSV)来连接B2F、F2B和B2B。可以使用层间过孔(Inter Layer Via，ILV)来连接F2F。
现在可适当地进行有关标准半导体工艺的讨论。
如本文中所使用的，“第0层源晶圆”是指由使用标准2D制造工艺制造的晶体管和互连件组成的完全填充(fully populated)的晶圆。该层还包括相关的对准标记，并形成了最终晶圆级三维(3D)集成电路(integrated circuit，IC)堆叠的起始层。
如本文中所使用的，“第k层源晶圆”是指由使用标准2D制造工艺在晶圆上制造的晶体管和互连件组成的完全填充的晶圆，该晶圆包括至少一个牺牲层，例如硅下的掩埋氧化物。该层还包括相关的对准标记，并被组装到第(k-1)层上并且是3D-IC堆叠体的一部分。该层的组装可以一步完成(一次性拾取所有2D管芯)，也可以分多个步骤进行，其中从第k层晶圆上拾取单个2D管芯阵列或多个2D管芯阵列，并将其精确放置在第(k-1)层晶圆上。
在一个实施方案中，执行所述组装以在第k层晶圆的每个2D管芯与第(k-1)层晶圆的对应2D管芯之间，实现亚50纳米(sub-50nm)的套刻、亚30纳米的套刻、亚20纳米的套刻、亚10纳米的套刻或者甚至亚5纳米的套刻。
参考图1，图1示出了根据本发明的实施方案的示例性第k层源晶圆100，其示出了多种2D管芯排列。
参考图1，第k层源晶圆100包括作为单个2D管芯的2D管芯阵列101、作为2D管芯连续岛的2D管芯阵列102以及作为一组岛的2D管芯阵列103。
如本文中所使用的，“2D管芯”是指三维(3D)片上系统(SoC)的单层，其中该3D-SoC包括至少两个以三维排列精确堆叠的2D管芯。这些2D管芯是使用标准的2D半导体制造工艺制造的。在一个实施方案中，2D管芯的厚度可小于10微米。由于研磨工艺引起的缺陷，使用标准的晶圆减薄工艺(例如背面研磨)变薄的晶圆预计将保持15微米以上的厚度。但是，使用非研磨工艺制造的2D管芯的厚度可以显著小于当前的厚度极限。
如本文中所使用的，“2D管芯阵列”是指单个2D管芯(参见2D管芯阵列101)或从其源晶圆(例如，第k层)集中移走，并且集中地精确组装到前一晶圆(第(k-1)层)上的一组2D管芯，其中k>1。该2D管芯阵列可以包括形成连续组的2D管芯单个岛(参见2D管芯阵列102)。可替选地，2D管芯阵列可以包括多个2D管芯岛，其中，每个2D管芯岛形成连续组，但是这些岛不是连续的(参见2D管芯阵列103)。
如本文中所使用的，“套刻(overlay)”是指在晶圆上的每个点处定义的矢量。它是衬底几何图形上的点的矢量位置与套刻图案中对应点的矢量位置之差。套刻的普遍接受的量词是所述套刻矢量幅度的(均值+3*σ)值。
如本文中所使用的，“对准(Alignment)”是指两个重叠主体之间的一组刚体误差(平移和旋转)。
参考图2，图2示出了根据本发明的实施方案的将第k层2D管芯阵列(k＞1)堆叠到第1层2D管芯阵列上。
如图2所示，在一个实施方案中，第一层源晶圆201对应于具有三个元件203的绝缘体上硅晶圆202。在一个实施方案中，晶圆202包括层状的硅204-绝缘体(牺牲层)205-硅206衬底。在一个实施方案中，元件203是“原料(feedstock)”，其最常规的形式由晶体管、互连件和电介质的层组成。此外，在一个实施方案中，本文所使用的元件203可以包括SOI晶圆202的硅层204。它本身可以具有或可以不具有任何功能，但是当与其他元件203以及可能的附加互连件和介电层组装在一起时，它可以用于制造作业用ASIC。此外，掩模成本高的前端高分辨率器件层将留在元件203内。这是为了在多种多样ASIC器件的制造过程中分摊昂贵的掩模(用于高分辨率器件层)成本。
在一个实施方案中，元件203的宽度对应于数十毫米的2D管芯宽度。在一个实施方案中，通道宽度(street width)或“划线宽度(scribe width)”可为数百纳米至数十微米。在一个实施方案中，这种宽度对应于元件203的边界207。
图2所示的源晶圆层中的每一层，例如第二层......第n层(其中n是一个正整数)均与第1层201配置类似。因此，这些层中的每一层(简称为“第k层”，其中k为正整数)在本文中通常称为元件201。
如图2所示，源晶圆的层以交织的方式堆叠(翻转、面朝上、翻转、面朝上......)，形成了3D-IC堆叠体208，这将在下面更详细地讨论。
此外，图2示出了例如可以使用穿硅通孔(TSV)来连接B2F、F2B和B2B，并且可以使用层间通孔(ILV)来连接F2F。下面将提供关于包括第k层晶圆的这种特征的进一步描述。
在一个实施方案中，布置允许第k层二维(2D)管芯阵列(例如，2D管芯阵列102)和第(k-1)层2D管芯阵列(例如，2D管芯阵列102)之间进行经润滑的相对运动的流体，其中该流体允许第k层和第(k-1)层2D管芯阵列的精确套刻。在一个实施方案中，流体是气体、液体或其组合。在一个实施方案中，此类组合包括完全分开的气体和液体部分或均匀混合的气体和液体部分。
在一个实施方案中，第1层2D管芯阵列可以处在任何任意衬底上，但是随后的2D管芯阵列(可以被取放)需要下方的牺牲层，如图3A-3B所示。因此，在一个实施方案中，第k层2D管芯可能需要下方的氧化物层以实现最佳的器件功能(例如，完全耗尽(FullyDepleted，FD)-SOI和部分耗尽(Partially Depleted，PD)-SOI)。这将需要在更深水平的另一牺牲层来进行取放。在一个实施方案中，这些可通过Lapis
Figure BDA0002647383340000051
购得。
在一个实施方案中，2D管芯的宽度可为数十微米至数十毫米。
现参考图3A至3B，图3A至3B示出了根据本发明的实施方案的具有两个掩埋层(绝缘层和牺牲层，其可以由相同的材料构成，例如氧化硅)的第k层SOI晶圆的横截面。
如图3B所示，第k层SOI晶圆201的横截面示出了元件203可以由晶体管301、互连件302和电介质303组成。在一个实施方案中，元件203还包括硅层304。此外，如上文所讨论的，第k层2D管芯可能需要下方的氧化物层305以实现最佳的器件性能。
在一个实施方案中，如图3A所示，该2D管芯的厚度可为数十纳米至数十微米。
此外，在一个实施方案中，图3A示出了元件203的边界207。
可替选地，在一个实施方案中，第k层2D管芯可不需要如图4A至4B所示的下方氧化物。图4A至4B示出了根据本发明的实施方案的第k层SOI晶圆的另一横截面。
在这样的实施方案中，出于机械稳定性的目的，牺牲层可能需要停留在比标准PD-SOI晶圆中所见的深度更深的水平上。这些可以通过多种来源购得，例如
Figure BDA0002647383340000052
此外，在一个实施方案中，如图5A至5B所示，牺牲氧化物(用于取放)的深度与用于标准PD-SOI晶圆的深度相同。这些可通过多种来源购得，例如
Figure BDA0002647383340000053
图5A至5B示出了根据本发明的实施方案的第k层SOI晶圆的另一横截面。
如图5A至5B所示，在一个实施方案中，2D管芯的厚度为大约100纳米或更小。
现在可适当地进行有关3D集成电路(IC)的工艺和机械设计概念的讨论。
在一个实施方案中，一般适用的组装顺序与Sreenivasan等人在文献WO 2018/119451 A1(下文称为“Sreenivasan等人”)中描述的基本相同，其全部内容通过引用并入本文。例如，步骤如下：1.蚀刻和封装；2.批量蚀刻工艺(以方便后续取放)；3.拾取2D管芯阵列；4.将2D管芯阵列对准产品衬底；5.临时附接和绑定；6.重复3-5，直到完全组装好产品晶圆。
在一个实施方案中，如下所述，3D-IC的组装顺序可能需要对步骤2、4和5进行一些修改。
为了便于后续取放，需要对批量蚀刻工艺做出一些修改，以考虑已实现的堆叠类型(例如，F2F vs F2B vs B2F vs B2B)。关于B2F和B2B类型的堆叠，由于第k层晶圆不需要被翻转，因此Sreenivasan等人描述的批量蚀刻工艺就足够了。然而，对于F2F和F2B类型的堆叠方式，除了批量蚀刻外，还需要进行晶圆翻转步骤。此外，对于F2F类型的堆叠，需要剥离步骤来选择性地移除封装层以实现面对面的连接。取决于所使用的封装层的特定性质，这可以通过多种方式实现，例如，如果封装层由Al2O3构成，则可以使用定时缓冲氧化物蚀刻。或者，如果封装层由化学气相沉积(chemical vapor deposited，CVD)的无定形碳构成，则可以使用氧等离子体进行剥离。或者，如果封装层由多个层构成，例如，在CVD无定形碳之上有Al2O3，则可以依次进行氧等离子体步骤和缓冲氧化物蚀刻。在一个实施方案中，封装层保护在第k层晶圆和第(k-l)层晶圆中的2D管芯不受取放过程中使用的蚀刻剂的影响。在一个实施方案中，封装层与现有半导体制造技术(例如，互补型金属-氧化物-半导体(complementary metal-oxide-semiconductor，CMOS))和III-V半导体(例如，氮化镓、砷化镓))兼容。下面结合图6、图7A至图7D、图8和图9A至图9D讨论翻转和散装物料去除这两种不同的技术。
图6是根据本发明的实施方案的基于背面研磨方式的翻转和散装物料去除方法的流程图。图7A至图7D描绘了根据本发明的实施方案的使用图6中描述的步骤进行的翻转和散装物料去除的剖视图。
现参考图6并结合图7A至图7D，在步骤601中，如图7A所示剥离封装层(未示出)。此外，如图7A所示，通导孔701可用于加速蚀刻过程。在一个实施方案中，通导孔701用于蚀刻剂(例如，氢氟酸)以将2D管芯从晶圆中释放出来。在一个实施方案中，利用通导孔701来产生实现穿硅通孔(TSV)的导体。
在步骤602中，如图7B所示，翻转第k层晶圆201，并通过激光脱粘粘合剂703(可商购获得)将该第k层晶圆201附接到玻璃载体晶圆702上。
在步骤603中，如图7C所示，进行第k层晶圆201的背面研磨。
在步骤604中，使用诸如氢氟酸(HF)的酸来蚀刻牺牲层205。
图8是根据本发明的实施方案的基于剥离方式的翻转和散装物料去除方法的流程图。图9A至图9E描绘了根据本发明的实施方案的使用图8中描述的步骤进行的翻转和散装物料去除的剖视图。
现参考图8并结合图9A至图9D，在步骤801中，以形成如图9A和图9B所示的锥形柱(栓系件(tether))901的方式，在牺牲层205上进行定时的氢氟酸(HF)蚀刻。这些锥形栓绳901(将在后文讨论)能够便利取放步骤。此外，如图9A所示，通导孔701可用于加速蚀刻过程。
在步骤802中，如图9C所示，剥离封装层(未示出)。
在步骤803中，如图9D所示，翻转第k层晶圆201。
在步骤804中，如图9E所示，将经翻转的第k层晶圆201通过激光脱粘粘合剂903(可商购获得)附接到玻璃载体晶圆902上，并剥离硅层206和牺牲层205。
如下文所讨论的，本发明的原理还使得经拾取的2D管芯阵列相对于产品衬底对准并提供变形控制。
在一个实施方案中，可以基于是否同时组装单个或多个2D管芯来实现精确对准，这不同于Sreenivasan等人中讨论的方法。
在多个2D管芯的情况下，莫尔计量(moire metrology)需要参考的是覆层(superstate)，而不是被取放的单个2D管芯。这将需要在覆层的底表面上图案化对准标记。可以在覆层的仅角部(absolute corner)处图案化这些标记，也可以使其分布在整个区域。产品晶圆上需要相应的标记。可以使用热致动来实施一定量的2D管芯变形控制。另外，也可以在晶圆卡盘中实施热致动，以增加致动自由度。如果覆层材料对于用于计量的光(通常是可见光或红外光(IR))波长不透明，则可以在覆层中制造多个观察窗。或者，可以由透明材料(例如，可商购获得的SiC和/或蓝宝石(Al2O3))构建覆层。下面结合图10和图11A至图11B讨论涉及多个2D管芯的精确对准。
图10是根据本发明实施方案的用于多个经封装的2D管芯套刻和变形控制的方法1000的流程图。图11A至图11B描绘了根据本发明的实施方案的使用图10中所描述的步骤来提供多个经封装的2D管芯的套刻和变形控制的剖视图。
参考图10并结合图11A至图11B，在步骤1001中，当拾取的2D管芯1101(拾取的2D管芯，例如2D管芯阵列101、102、103)靠近产品晶圆1102时，首先如图11A所示进行粗略对准(course alignment)。图11A示出了具有对准标记1104和观察窗1105的覆层1103。
在步骤1002中，进行精细对准，将覆层1103的对准标记1104和观察窗1105与衬底中的对准标记1106对准。在一个实施方案中，可以使用通过热致动器1107的热致动来实施一定量的2D管芯变形控制。另外，可以在晶圆卡盘1108中实施热致动，热致动也用于增加致动自由度。
在单个2D管芯的情况下，除了上述方法之外，可以使用嵌入在第k层和第(k-l)层2D管芯1101中的IR敏感标记1201和IR透明覆层进行莫尔计量，如图12A至图12B所示。图12A至12B示出了根据本发明的实施方案的单个经拾取2D管芯的套刻和变形控制。
现参考图13，图13示出了根据本发明的实施方案的通过已经存在于经取放的2D管芯中的通导孔制成穿硅通孔(TSV)。如图13所示，第k层、第(k+l)层和第(k+2)层的排列方式是第(k+l)层被翻转且第(k+2)层面朝上。如图13进一步所示，通过域通导孔701制成穿硅通孔。
对于如静态随机存取存储器(SRAM)堆叠等应用来说，所需的TSV的密度可高达10000/mm。在这个TSV密度水平下，TSV的直径可为约20纳米至80纳米。可以潜在地通过已经存在于2D管芯中的通导孔701对这些TSV的一些或全部进行布线。
现参考图14A至图14C，图14A至14C示出了根据本发明的实施方案的用于临时附接和绑定的示例性过程。
在一个实施方案中，临时附接之后可进行绑定。在一个实施方案中，可以使用基于动态气垫的“慢着陆(slow landing)”方法。这种系统曾用于高精度空气轴承平台、硬盘驱动系统，并已被研究用于固体表面上的液滴滑行。在这种方法中，可以首先在第0层2D管芯的边缘上分配可紫外固化(UV-curable)的粘合剂薄层。所述粘合剂可以由挥发性和非挥发性组分的组合构成，其中，在极限情形下，粘合剂仅由非挥发性组分构成。由可紫外固化的粘合剂和/或挥发性组分组成的液体提供阻尼，从而显著最小化了第0层和第1层2D管芯之间的振动位移。当附接有第1层2D管芯的覆层靠近第0层管芯时，可以启动通过压力孔1401的气流。这将在2D管芯周围产生一个由空气或氮气构成的轴承(bearing)(以获得惰性环境)。覆层的z力和上述轴承流速的组合旋钮(combined knob)可用于控制“软着陆(softlanding)”。同时，当覆层1103被压下时，可以进行粗略对准校正。同时，在正在被堆叠的2D管芯之间产生第二气垫1402。该第二气垫1402可以在精确对准校正期间在2D管芯之间提供额外的润滑。
此外，空气从该气垫的向外流动将确保粘合剂(位于边缘)中的挥发性成分不会污染2D管芯主体中的金属-金属触点1403。此外，可以通过使用具有z方向压电致动器的覆层1103来改变2D管芯的形貌(topography)以控制第二气垫1402的流速。这种系统先前已经被阐述过。一旦2D管芯接触，则可以进行全面(blanket)紫外线曝光1404以固化边缘放置的粘合剂。为了进一步固定2D管芯，可以进行金属触点1403的表面活化。这种工艺之前已经在室温下的金属-金属绑定中展示过，包括诸如铜、钨和铝等金属。铜的表面活化可以通过对铜表面进行氩离子处理来实现。在一个实施方案中，假设上述空气轴承中使用的所有空气都是半导体级清洁干燥空气。或者，如果轴承中使用氮气，也认为该氮气是半导体级的、干净并且干燥。在一个实施方案中，表面活化的铜在活化过程之后一直保持在惰性环境中直到绑定步骤(包括从工具-工具的运输和在每个其进行加工所处于的工具中)。在一个实施方案中，真空孔1405可用于实现基于真空的拾取机构。
现在可适当地进行有关实现3D-IC片上系统(SoC)所需的设计和电子设计自动化(EDA)/计算机辅助设计(computer-aided design，CAD)流程的讨论。通常，2D ASIC SoC由数十亿个晶体管构成，这些晶体管被最佳地放置以满足性能/速度、面积和功率规格。为了有效设计2D ASIC SoC，即满足设计规格、降低上市周转时间(turn-around time，TAT)，已经存在简化设计过程的商业EDA CAD工具。然而，目前还不存在用于3D-IC ASIC设计的EDA工具。
典型的ASIC SoC可被大致分为以下部分：逻辑(CPU、GPU、调制解调器(Modem)等)、存储器/高速缓存(静态随机存取存储器(SRAM)、嵌入式动态随机存取存储器(embeddeddynamic random access memory，eDRAM)等)、第三方IP模块、模拟IP、IO等。3D SoC设计旨在实现相同功能的SoC，同时减少占用空间(foot print)并提高其在缩短存储器存取时间和延迟，使带宽更高、容量更大(以Mbit/mm2计)、频率更高(由于互连延迟时间更短)等方面的性能。
典型的3D SoC，在本文中也可称为“纳米精度对准的3D堆叠型集成电路(Nano-precision aligned 3D Stacked Integrated Circuit，N3SI)”，包括n个晶体管基层，其中n>1。在一个实施方案中，使用亚50纳米套刻取放方法，以三维方式设计和制造具有逻辑和存储器电路的专用集成电路(ASIC)片上系统(SoC)，该亚50纳米套刻取放方法允许实现逻辑和存储器电路的精确套刻。每个基层可以有m个金属层，其中，m＞＝1，并且每个基层可以不同。3D堆叠中的基层可以相对于彼此以以下配置中的任一种布置：面对面、面对背、背对背等。如果基层是面对面配置，则可以使用层间通孔(ILV)来实现跨不同基层的连接；如果基层是面对背或背对背配置，则可以使用纳米级穿硅通孔(nano-TSV)来实现跨不同基层的连接。3D SoC可以使用以下任何设计方法的组合来设计：具有3D存储器实现的2D逻辑实现、具有2D存储器实现的3D逻辑实现、具有3D存储器实现的3D逻辑实现等。3D逻辑实现既可以在块/分区水平执行，也可以在平面水平执行。在3D块水平的逻辑实现中，使用2D工具对分区进行合成和布线，但是将不同的分区布置在不同的基层中。这种方法只需要改变顶层SoC设计，而3D SoC的块级设计与2D SoC保持一致。因此，这种方法更容易实现。在平面级3D逻辑实现中，也以3D方式实现分区，即，分区内的单元被布置在多个基层中。下面分别讨论3D逻辑实现和3D存储器设计实现。由TSV和HF孔造成的面积开销也可以通过空间优化算法进行优化。
现在讨论3D-IC逻辑实现的电子设计自动化(EDA)设计方法。图15示出了根据本发明的一个实施方案的用于逻辑实现的常规2D ASIC EDA流程。合成在前端设计阶段执行，而后端设计阶段执行布局、CTS前优化(pre-CTS optimization)、时钟树合成(CTS)、布线、布线后优化(post route optimization)、签核分析和设计验证。
用于3D-IC SoC的本发明EDA方法也类似于2D ASIC的流程。该方法试图重新使用大多数现有的商业2D EDA工具，同时使用了一些内部开发的解决方案。这种流程在本文中被称为“N3 SI EDA流程”。以下各小节描述了N3 SI EDA流程设计步骤。
3D-IC SoC的合成
3D-IC SoC的合成利用了商用2D合成工具。在第一遍次(pass)，完全按照2D SoC中的方式合成设计。一旦执行了布局，则执行3D布局感知合成。在此合成遍次中，由于该工具具有3D布局信息以获得精确的互连负载和延迟，因此它能更佳地合成单元。该工艺流程也类似于2D布局感知合成，但是，在本实施方案中，布局信息是三维的。
3D-IC SoC的布局
本节讨论逻辑/标准单元的3D布局。在本发明的方法中，首先将设计网表划分为多个模块，使得每个模块网表由待布置在3D-IC SoC堆叠体的不同层上的逻辑单元等组成。然后，使用商用2D EDA工具对3D堆叠体的指定层中的每个模块进行2D布局。可以使用内部解决方案来划分网表，这些解决方案使用标准的划分算法，如最小割法(FM Min-Cut)、最小流法(Min-Flow)等。在划分中生成的模块包括输入/输出端口，这些端口不仅可以位于模块外围，还可以位于模块中的任何位置。因此，内部开发的软件使用标准的划分算法来生成这些端口的位置。多个模块通过这些端口传输信号。这些端口可以通过层间通孔(ILV)或纳米级穿硅通孔(nano-TSV)连接。可基于ILV和TSV的热稳定性和机械稳定性来约束这些端口的位置。一旦确定了端口的位置，时序预算和端口位置将被提供至2D布局工具中，使每个模块的布局独立执行，同时确保总体时序和性能指标得到满足。为了确保合法的单元布局，在TSV或HF孔通过的模块区域中形成布局或布线阻断。也就是说，内部开发的软件使用标准划分算法来生成布局或布线阻断，以例如避免ILV/TSV位置处的设计规则检查(Design RuleChecking，DRC)问题。
3D-IC SoC的CTS
可以使用现有的2D EDA布局和布线(placement and route，P&R)工具来执行3DSoC的时钟树合成(CTS)。一旦将设计划分并布置到多个模块中，就可以分别针对每个模块构建和优化时钟树。然而，3D时钟树的挑战在于，在考虑到其上可构建3D时钟树的多个晶圆间的工艺变化时，确保没有设置(setup)、保持(hold)等违规行为。有多种方法可以解决或避免这个问题。一种可能的解决方案是将启动和捕获触发器的布局约束在同一层上，即需要将数据路径的启动和捕获触发器布置在同一层上。这可以通过内部网表划分工具来实现。另一个解决方案是包含高余裕度，以确保在最坏的工艺变化情况下不存在违规。
3D-IC SoC的布线
3D-IC SoC的布线方法包括每个模块内的2D布线，以及使用ILV和纳米TSV在多个模块间布线。下面将讨论可以精确确定的电阻值和电容值。3D-IC布线方法与2D布线方法保持一致。每个模块的布线可以单独使用2D P&R工具实现。为了确保没有设计规则检查(DRC)故障，在设有ILV和TSV互连件的区域中形成布线阻断。
3D-IC SoC的寄生提取
3D SoC的寄生提取的设计方法不同于2D ASIC。由于TSV和ILV，电阻值和电容值会有显著变化。商用EDA工具不能执行3D提取。然而，本发明的实施方案利用了使用现有2D提取器的3D提取流程。在这个流程中，首先，以流的形式输出每个模块或层的布局信息(layout information)。然后，所有模块的布局/布线数据(layout/route data)被流式传输到布局编辑器工具(如
Figure BDA0002647383340000101
)中。在流式传输时，如果需要，可以翻转任何特定模块的布局，使其看起来与3D SoC堆叠体相同。然后，在该布局上运行提取器。所获得的电阻值和电容值已考虑到了3D布局，考虑到了TSV和ILV，并且被预期为准确的。
现在讨论静态随机存取存储器(SRAM)的3D设计实现。典型的SRAM包括具有字线和位线的位单元阵列、感测放大器、列和行解码器、定时器电路、IO、其他外围电路等。存在多种SRAM配置(如蝶形配置、单面配置等)以布置SRAM的设计元件。这些配置在实现复杂性、访问时间、延迟等方面有所不同。图16示出了根据本发明实施方案的2D单面SRAM配置。SRAM配置包括基本存储器设计元件，例如SRAM单元的位阵列1601、位线1602、字线1603、IO单元1604、定时器电路1605、感测放大器1606和解码器1607。
与2D SRAM配置类似，3D SRAM可以根据设计需要设计成多种配置。3D eDRAM也类似于3D SRAM方法，可以设计类似的eDRAM配置。如图17所示，一种可能的3D单面SRAM配置是独立SRAM阵列的3D堆叠管芯。图17示出了根据本发明的实施方案的3D独立SRAM管芯堆叠。
在这种3D SRAM配置中，每一层都实现了可自我维持的2D单面SRAM。数据输入、功率和控制信号被提供到以3D配置堆叠的每个2D SRAM中，并且从每一层获得输出数据信号。将所有层的数据输出组合在一起，形成完整的3D SRAM输出。例如，如图17所示，32位Din数据总线信号被分成4个8位数据总线信号，并被提供到4个层中的每一层中。每层的数据输出Dout由8位输构成，且将4层的数据输出Dout组合成32位输出信号。
其它可能的3D单面SRAM配置之一是图18所示的根据本发明的实施方案的3D仅位单元堆叠SRAM。
在这种类型的3D SRAM配置中，基层(即层1)包括具有位线1802和字线1803的位单元阵列1801、控制和外围电路元件(例如，IO单元1804)、定时器电路1805、感测放大器1806和解码器1807。堆叠的3D层仅包括位单元阵列、位线和字线。在一个实施方案中，与2D配置相比，用于3D SRAM的基层中的控制电路预期具有更多的列解码器。类似于单面SRAM设计，其他2D SRAM配置(如蝶形配置等)也可以以3D实现。
在3D仅位单元堆叠式SRAM中，有多种方法可以根据设计规范对其进行设计。在其中一种配置中，每层包含与2D SRAM的位单元阵列大小相同的位单元阵列。在3D SRAM中，位线和字线的长度、带宽、占用空间等与2D SRAM中相同，但是存储器容量(即阵列位单元密度)是2D SRAM中的存储器容量的n倍，其中，n是层数。可增加更多的感测放大器，以增加存储器带宽，从而对这种设计配置进行略微修改。图19示出了根据本发明的实施方案的用于3D仅位单元堆叠的SRAM的垂直位线横截面。
如图19所示，本示例不使用列解码器来选择位线层。然而，由于位线长度较小，存储器存取时间预计会被缩短，这最终会减小时间常数RC，其中R是电阻，C是电容。为了选择特定层的位线，可以将解码器添加到该设计配置中。
在另一种可能的3D仅位单元堆叠SRAM设计配置中，在保持存储器容量(即阵列位单元密度)不变的同时，减少了占用空间/面积。在该配置中，第一基层包括与2D SRAM配置中使用的控制电路相同的控制电路。在3D配置中，位阵列的占用空间可以被减少(在2D配置中，其通常占SRAM面积的70％)。位单元阵列面积可以通过除以n得到，其中，n(n>1)是位单元阵列层数。在这种配置中，位线和字线的长度将更短，并带有额外的列解码器。但是，预计这种类型的存储器配置将导致较短的存储器存取时间。
利用本发明的原理，现在可以制造三维(3D)堆叠式集成电路。在一个实施方案中，利用取放策略堆叠具有使用标准二维(2D)半导体制造技术制造的器件层的源晶圆。该源晶圆可以以顺序或平行方式堆叠。堆叠方式可以是面对面、面对背、背对面或背对背。可以利用穿硅通孔(TSV)连接以面对背、背对面或背对背方式堆叠的源晶圆。或者，可以使用层间通孔(ILV)连接以面对面方式堆叠的源晶圆。
为了说明的目的，已经给出了本发明的多种实施方案的描述，但是这些描述并不旨在穷举或者限制所公开的实施方案。在不脱离所描述的实施方案的范围和精神的情况下，对于本领域的普通技术人员来说，多种修改和变化是显然的。本文选择使用的术语是为了最好地解释实施方案的原理、实际应用或相对于市场上可见的技术所进行的技术改进，或者使本领域的其他普通技术人员能够理解本文公开的实施方案。

Claims (30)

1.一种用于制造三维(3D)片上系统(SoC)的方法，所述方法包括：
将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，所述第(k-1)层晶圆填充有2D管芯，其中，所述k是大于1的正整数，其中，所述2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛；和
布置允许所述第k层2D管芯阵列与所述第(k-1)层2D管芯阵列之间进行经润滑的相对运动的流体，其中，所述流体允许所述第k层和第(k-1)层2D管芯阵列的精确套刻。
2.根据权利要求1所述的方法，其中，执行所述组装以实现以下中的一种：在第k层晶圆的每个2D管芯与所述第(k-1)层晶圆的对应2D管芯之间，实现亚100纳米的套刻、亚50纳米的套刻、亚30纳米的套刻、亚20纳米的套刻、亚10纳米的套刻和亚5纳米的套刻。
3.根据权利要求1所述的方法，其中，所述流体包括以下之一：气体、液体及其组合，其中，所述组合包括完全分开的气体和液体部分或均匀混合的气体和液体部分。
4.根据权利要求1所述的方法，其中，所述2D管芯包括蚀刻剂的通导孔，以将所述2D管芯从所述第(k-1)层晶圆中释放出来。
5.根据权利要求4所述的方法，还包括：
利用所述通导孔产生在所述3D SoC中实现穿硅通孔的导体。
6.根据权利要求1所述的方法，其中，所述SoC包括专用集成电路(ASIC)系统，其中，所述ASIC系统包括利用取放方法以三维(3D)方式设计和制造的逻辑和存储器电路，所述取放方法允许实现所述逻辑和存储器电路的精确套刻。
7.根据权利要求6所述的方法，其中，所述ASIC系统还包括：
n个基层，其中，所述n大于1，其中，所述n个基层中的一个或多个以以下一种或多种配置布置：面对面、面对背和背对背。
8.根据权利要求6所述的方法，其中，所述ASIC系统是使用以下设计方法中的任一种设计的：具有三维(3D)存储器实现的二维(2D)逻辑实现、具有2D存储器实现的3D逻辑实现以及具有3D存储器实现的3D逻辑实现。
9.根据权利要求6所述的方法，其中，所述ASIC系统用于以下3D静态随机存取存储器(SRAM)配置中的一种或多种：3D独立堆叠式SRAM和3D仅位单元堆叠式SRAM。
10.一种用于制造三维(3D)片上系统(SoC)的方法，所述方法包括：
将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，所述第(k-1)层晶圆装填充有2D管芯，其中，所述k是大于1的正整数，其中，所述2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛；和
提供封装层，用于保护在第k层晶圆和所述第(k-1)层晶圆中的每一层中的2D管芯免受在取放过程中所使用的蚀刻剂的影响。
11.根据权利要求10所述的方法，其中，所述封装层与互补金属氧化物半导体(CMOS)和/或III-V半导体兼容。
12.根据权利要求10所述的方法，其中，执行所述组装以实现以下中的一种：在所述第k层晶圆的每个2D管芯与所述第(k-1)层晶圆的对应2D管芯之间，实现亚100纳米的套刻、亚50纳米的套刻、亚30纳米的套刻、亚20纳米的套刻、亚10纳米的套刻和亚5纳米的套刻。
13.根据权利要求10所述的方法，其中，所述2D管芯包括蚀刻剂的通导孔，以将所述2D管芯从所述第(k-1)层晶圆中释放出来。
14.根据权利要求13所述的方法，还包括：
利用所述通导孔产生在所述3D SoC中实现穿硅通孔的导体。
15.根据权利要求10所述的方法，其中，所述SoC包括专用集成电路(ASIC)系统，其中，所述ASIC系统包括利用所述取放方法以三维(3D)方式设计和制造的逻辑和存储器电路，所述取放方法允许实现所述逻辑和存储器电路的精确套刻。
16.根据权利要求15所述的方法，其中，所述ASIC系统还包括：
n个基层，其中，所述n大于1，其中，所述n个基层中的一个或多个以以下一种或多种配置布置：面对面、面对背和背对背。
17.根据权利要求15所述的方法，其中，所述ASIC系统是使用以下设计方法中的任一种设计的：具有三维(3D)存储器实现的二维(2D)逻辑实现、具有2D存储器实现的3D逻辑实现以及具有3D存储器实现的3D逻辑实现。
18.根据权利要求15所述的方法，其中，所述ASIC系统用于以下3D静态随机存取存储器(SRAM)配置中的一种或多种：3D独立堆叠式SRAM和3D仅位单元堆叠式SRAM。
19.一种用于制造三维(3D)片上系统(SoC)的方法，所述方法包括：
将第k层二维(2D)管芯阵列组装到第(k-1)层晶圆的第(k-1)层2D管芯阵列上，其中，所述第(k-1)层晶圆填充有2D管芯，其中，所述k是大于1的正整数，其中，所述2D管芯阵列包括单个2D管芯、形成2D管芯连续组的单个2D管芯岛、或多个2D管芯岛，其中，所述2D管芯的厚度小于10微米。
20.根据权利要求19所述的方法，其中，执行所述组装以实现以下其中之一：在第k层晶圆的每个2D管芯与所述第(k-1)层晶圆的对应2D管芯之间，实现亚100纳米的套刻、亚50纳米的套刻、亚30纳米的套刻、亚20纳米的套刻、亚10纳米的套刻和亚5纳米的套刻。
21.根据权利要求19所述的方法，其中，所述2D管芯包括蚀刻剂的通导孔，以将所述2D管芯从所述第(k-1)层晶圆中释放出来。
22.根据权利要求21所述的方法，还包括：
利用所述通导孔产生在所述3D SoC中实现穿硅通孔的导体。
23.根据权利要求19所述的方法，其中，所述SoC包括专用集成电路(ASIC)系统，其中，所述ASIC系统包括利用取放方法以三维(3D)方式设计和制造的逻辑和存储器电路，所述取放方法允许实现所述逻辑和存储器电路的精确套刻。
24.根据权利要求23所述的方法，其中，所述ASIC系统还包括：
n个基层，其中，所述n大于1，其中，所述n个基层中的一个或多个以以下一种或多种配置布置：面对面、面对背和背对背。
25.根据权利要求23所述的方法，其中，所述ASIC系统是使用以下设计方法中的任一种设计的：具有三维(3D)存储器实现的二维(2D)逻辑实现、具有2D存储器实现的3D逻辑实现以及具有3D存储器实现的3D逻辑实现。
26.根据权利要求23所述的方法，其中，所述ASIC系统用于以下3D静态随机存取存储器(SRAM)配置中的一种或多种：3D独立堆叠式SRAM和3D仅位单元堆叠式SRAM。
27.一种用于设计三维(3D)专用集成电路(ASIC)片上系统(SoC)逻辑电路的电子设计自动化(EDA)方法，包括：
集成有二维(2D)EDA解决方案的软件的组合，其中，所述软件包括网表划分算法，以将3D设计网表划分为2D模块，其中，所述2D EDA解决方案用于执行以下一项或多项：合成、3D布局感知合成、布局、时钟树合成(CTS)、布线、设计验证和签核分析。
28.根据权利要求27所述的EDA方法，其中，所述算法执行以下一项或多项：生成端口的位置以及生成布局阻断或布线阻断。
29.根据权利要求28所述的EDA方法，其中，基于层间通孔(ILV)和穿硅通孔(TSV)的热稳定性和机械稳定性来约束所述端口的所述位置。
30.根据权利要求27所述的EDA方法，还包括：
将布局数据或布线数据流式传输至布局编辑器工具中，其中，响应于使特定模块的布局看起来与3D SoC堆叠相同，将所述特定模块的所述布局翻转；以及
获得考虑所述布局并考虑了ILV和TSV的电阻值和电容值。
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