KR101931419B1 - 구성가능한 핀을 갖는 3차원 플래시 nor 메모리 시스템 - Google Patents

구성가능한 핀을 갖는 3차원 플래시 nor 메모리 시스템 Download PDF

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KR101931419B1
KR101931419B1 KR1020167017759A KR20167017759A KR101931419B1 KR 101931419 B1 KR101931419 B1 KR 101931419B1 KR 1020167017759 A KR1020167017759 A KR 1020167017759A KR 20167017759 A KR20167017759 A KR 20167017759A KR 101931419 B1 KR101931419 B1 KR 101931419B1
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delete delete
die
tsv
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dies
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KR20160094423A (ko
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히예우 반 트란
헝 큐옥 구엔
마크 라이텐
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실리콘 스토리지 테크놀로지 인크
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H01L24/13—
    • H01L24/14—
    • H01L24/16—
    • H01L25/0652—
    • H01L25/0657—
    • H01L25/18—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
KR1020167017759A 2013-12-02 2014-11-06 구성가능한 핀을 갖는 3차원 플래시 nor 메모리 시스템 Active KR101931419B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/094,595 US20150155039A1 (en) 2013-12-02 2013-12-02 Three-Dimensional Flash NOR Memory System With Configurable Pins
US14/094,595 2013-12-02
PCT/US2014/064381 WO2015084534A1 (en) 2013-12-02 2014-11-06 Three-dimensional flash nor memory system with configurable pins

Publications (2)

Publication Number Publication Date
KR20160094423A KR20160094423A (ko) 2016-08-09
KR101931419B1 true KR101931419B1 (ko) 2018-12-20

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KR1020167017759A Active KR101931419B1 (ko) 2013-12-02 2014-11-06 구성가능한 핀을 갖는 3차원 플래시 nor 메모리 시스템

Country Status (7)

Country Link
US (2) US20150155039A1 (https=)
EP (1) EP3078028A1 (https=)
JP (1) JP6670749B2 (https=)
KR (1) KR101931419B1 (https=)
CN (1) CN105793928B (https=)
TW (1) TWI550926B (https=)
WO (1) WO2015084534A1 (https=)

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Also Published As

Publication number Publication date
US20170323682A1 (en) 2017-11-09
TWI550926B (zh) 2016-09-21
KR20160094423A (ko) 2016-08-09
JP2017502444A (ja) 2017-01-19
CN105793928B (zh) 2020-12-25
TW201532326A (zh) 2015-08-16
JP6670749B2 (ja) 2020-03-25
US20150155039A1 (en) 2015-06-04
EP3078028A1 (en) 2016-10-12
WO2015084534A1 (en) 2015-06-11
CN105793928A (zh) 2016-07-20
US10373686B2 (en) 2019-08-06

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