KR101918166B1 - 결정된 파장의 광속을 이용하여 기판을 처리하기 위한 프로세스 및 대응하는 기판 - Google Patents

결정된 파장의 광속을 이용하여 기판을 처리하기 위한 프로세스 및 대응하는 기판 Download PDF

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KR101918166B1
KR101918166B1 KR1020137005906A KR20137005906A KR101918166B1 KR 101918166 B1 KR101918166 B1 KR 101918166B1 KR 1020137005906 A KR1020137005906 A KR 1020137005906A KR 20137005906 A KR20137005906 A KR 20137005906A KR 101918166 B1 KR101918166 B1 KR 101918166B1
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South Korea
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layer
substrate
embedded
embedded layer
irradiation
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Expired - Fee Related
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KR1020137005906A
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Korean (ko)
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KR20140019281A (ko
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미쉘 브뤼엘
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소이텍
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10P34/42—
    • H10P50/00—
    • H10P54/00—
    • H10P95/11—

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Laser Beam Processing (AREA)
KR1020137005906A 2010-09-10 2011-09-20 결정된 파장의 광속을 이용하여 기판을 처리하기 위한 프로세스 및 대응하는 기판 Expired - Fee Related KR101918166B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1057211A FR2964788B1 (fr) 2010-09-10 2010-09-10 Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant
FR1057211 2010-09-10
PCT/EP2011/065259 WO2012031998A1 (en) 2010-09-10 2011-09-05 Process for treating a substrate using a luminous flux of determined wavelength, and corresponding substrate

Publications (2)

Publication Number Publication Date
KR20140019281A KR20140019281A (ko) 2014-02-14
KR101918166B1 true KR101918166B1 (ko) 2018-11-13

Family

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KR1020137005906A Expired - Fee Related KR101918166B1 (ko) 2010-09-10 2011-09-20 결정된 파장의 광속을 이용하여 기판을 처리하기 위한 프로세스 및 대응하는 기판

Country Status (7)

Country Link
US (2) US9190314B2 (enExample)
EP (1) EP2614519B1 (enExample)
JP (1) JP5952281B2 (enExample)
KR (1) KR101918166B1 (enExample)
CN (1) CN103201825A (enExample)
FR (1) FR2964788B1 (enExample)
WO (1) WO2012031998A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2964788B1 (fr) 2010-09-10 2015-05-15 Soitec Silicon On Insulator Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234356A (en) 1979-06-01 1980-11-18 Bell Telephone Laboratories, Incorporated Dual wavelength optical annealing of materials
US4456490A (en) 1983-03-09 1984-06-26 Westinghouse Electric Corp. Laser annealing of MIS devices by back surface laser treatment
WO2010052408A1 (fr) 2008-11-04 2010-05-14 S.O.I.Tec Silicon On Insulator Technologies Procede et dispositif de chauffage d'une couche d'une plaque par amorcage et flux lumineux.

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR757986A (fr) 1932-07-04 1934-01-05 Thomson Houston Comp Francaise Perfectionnements aux tubes électroniques et à leurs circuits
JP2008135436A (ja) * 2006-11-27 2008-06-12 Seiko Epson Corp 剥離方法、半導体デバイス及び電子機器
JP5286684B2 (ja) * 2007-03-28 2013-09-11 セイコーエプソン株式会社 薄膜層の剥離方法、薄膜デバイスの転写方法
FR2921752B1 (fr) * 2007-10-01 2009-11-13 Aplinov Procede de chauffage d'une plaque par un flux lumineux.
FR2964788B1 (fr) 2010-09-10 2015-05-15 Soitec Silicon On Insulator Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234356A (en) 1979-06-01 1980-11-18 Bell Telephone Laboratories, Incorporated Dual wavelength optical annealing of materials
US4456490A (en) 1983-03-09 1984-06-26 Westinghouse Electric Corp. Laser annealing of MIS devices by back surface laser treatment
WO2010052408A1 (fr) 2008-11-04 2010-05-14 S.O.I.Tec Silicon On Insulator Technologies Procede et dispositif de chauffage d'une couche d'une plaque par amorcage et flux lumineux.

Also Published As

Publication number Publication date
FR2964788B1 (fr) 2015-05-15
JP2013541197A (ja) 2013-11-07
WO2012031998A1 (en) 2012-03-15
JP5952281B2 (ja) 2016-07-13
KR20140019281A (ko) 2014-02-14
US20130154065A1 (en) 2013-06-20
US9190314B2 (en) 2015-11-17
CN103201825A (zh) 2013-07-10
FR2964788A1 (fr) 2012-03-16
EP2614519A1 (en) 2013-07-17
US20160056247A1 (en) 2016-02-25
EP2614519B1 (en) 2015-07-01
US9564496B2 (en) 2017-02-07

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