KR101570267B1 - 메모리 기록 동작 방법들 및 회로들 - Google Patents

메모리 기록 동작 방법들 및 회로들 Download PDF

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Publication number
KR101570267B1
KR101570267B1 KR1020127033683A KR20127033683A KR101570267B1 KR 101570267 B1 KR101570267 B1 KR 101570267B1 KR 1020127033683 A KR1020127033683 A KR 1020127033683A KR 20127033683 A KR20127033683 A KR 20127033683A KR 101570267 B1 KR101570267 B1 KR 101570267B1
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KR
South Korea
Prior art keywords
word line
type
transistors
cells
state
Prior art date
Application number
KR1020127033683A
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English (en)
Korean (ko)
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KR20130038883A (ko
Inventor
제이딥 피. 쿨카르니
무하마드 엠. 켈라
비비체 엠. 게우스켄즈
아리지트 레이초우두리
타나이 카르니크
비벡 케이. 드
Original Assignee
인텔 코포레이션
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Publication date
Application filed by 인텔 코포레이션 filed Critical 인텔 코포레이션
Publication of KR20130038883A publication Critical patent/KR20130038883A/ko
Application granted granted Critical
Publication of KR101570267B1 publication Critical patent/KR101570267B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
KR1020127033683A 2010-06-25 2011-06-15 메모리 기록 동작 방법들 및 회로들 KR101570267B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/823,642 US8467263B2 (en) 2010-06-25 2010-06-25 Memory write operation methods and circuits
US12/823,642 2010-06-25
PCT/US2011/040458 WO2011163022A2 (fr) 2010-06-25 2011-06-15 Procédés et circuits pour opération d'écriture en mémoire

Publications (2)

Publication Number Publication Date
KR20130038883A KR20130038883A (ko) 2013-04-18
KR101570267B1 true KR101570267B1 (ko) 2015-11-18

Family

ID=45352459

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127033683A KR101570267B1 (ko) 2010-06-25 2011-06-15 메모리 기록 동작 방법들 및 회로들

Country Status (7)

Country Link
US (1) US8467263B2 (fr)
EP (1) EP2586029B1 (fr)
JP (1) JP5642269B2 (fr)
KR (1) KR101570267B1 (fr)
CN (2) CN102959633B (fr)
TW (1) TWI489484B (fr)
WO (1) WO2011163022A2 (fr)

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* Cited by examiner, † Cited by third party
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US8467263B2 (en) * 2010-06-25 2013-06-18 Intel Corporation Memory write operation methods and circuits
JP5846789B2 (ja) * 2010-07-29 2016-01-20 株式会社半導体エネルギー研究所 半導体装置
US8730713B2 (en) * 2011-09-12 2014-05-20 Qualcomm Incorporated SRAM cell writability
US8908439B2 (en) 2012-09-07 2014-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Adaptive word-line boost driver
US9190144B2 (en) * 2012-10-12 2015-11-17 Micron Technology, Inc. Memory device architecture
US9030863B2 (en) 2013-09-26 2015-05-12 Qualcomm Incorporated Read/write assist for memories
US9245602B2 (en) * 2013-12-10 2016-01-26 Broadcom Corporation Techniques to boost word-line voltage using parasitic capacitances
CN104900255B (zh) * 2014-03-03 2018-03-09 台湾积体电路制造股份有限公司 用于双端口sram的升压系统
US9552854B1 (en) * 2015-11-10 2017-01-24 Intel Corporation Register files including distributed capacitor circuit blocks
CN107591178B (zh) * 2016-07-06 2021-01-15 展讯通信（上海）有限公司 静态随机存储器阵列的字线抬升方法及装置
US11170830B2 (en) * 2020-02-11 2021-11-09 Taiwan Semiconductor Manufacturing Company Limited Word line driver for low voltage operation
US12087398B2 (en) * 2021-07-29 2024-09-10 Changxin Memory Technologies, Inc. Wordline driver circuit and memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241058A (ja) * 2003-02-07 2004-08-26 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2008021371A (ja) * 2006-07-13 2008-01-31 Renesas Technology Corp 半導体回路
US20080316836A1 (en) * 2007-06-22 2008-12-25 Tan Soon Hwei Ground biased bitline register file

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JPS63244395A (ja) * 1987-03-30 1988-10-11 Mitsubishi Electric Corp ダイナミツク型半導体記憶装置
JP3376594B2 (ja) * 1991-11-20 2003-02-10 日本電気株式会社 行デコーダ
JP3080829B2 (ja) * 1994-02-17 2000-08-28 株式会社東芝 カスケード型メモリセル構造を有した多バンクシンクロナスメモリシステム
KR100252476B1 (ko) * 1997-05-19 2000-04-15 윤종용 플레이트 셀 구조의 전기적으로 소거 및 프로그램 가능한 셀들을 구비한 불 휘발성 반도체 메모리 장치및 그것의 프로그램 방법
KR100247228B1 (ko) * 1997-10-04 2000-03-15 윤종용 워드라인과 자기정렬된 부우스팅 라인을 가지는불휘발성 반도체 메모리
US6097651A (en) * 1999-06-30 2000-08-01 Quicklogic Corporation Precharge circuitry in RAM circuit
JP2001312888A (ja) * 2000-04-28 2001-11-09 Texas Instr Japan Ltd 半導体記憶装置
US6426914B1 (en) * 2001-04-20 2002-07-30 International Business Machines Corporation Floating wordline using a dynamic row decoder and bitline VDD precharge
JP2004087044A (ja) 2002-08-28 2004-03-18 Fujitsu Ltd 半導体記憶装置およびその制御方法
KR100586841B1 (ko) * 2003-12-15 2006-06-07 삼성전자주식회사 가변 딜레이 제어 방법 및 회로
KR100534216B1 (ko) 2004-06-18 2005-12-08 삼성전자주식회사 반도체 메모리에서의 워드라인 드라이버 회로 및 그에따른 구동방법
US7180818B2 (en) * 2004-11-22 2007-02-20 International Business Machines Corporation High performance register file with bootstrapped storage supply and method of reading data therefrom
KR100894487B1 (ko) * 2007-06-08 2009-04-22 주식회사 하이닉스반도체 워드라인 구동회로, 이를 포함하는 반도체 메모리장치 및그 테스트방법
US20090175210A1 (en) 2007-07-26 2009-07-09 Qualcomm Incorporated Multiplexing and transmission of multiple data streams in a wireless multi-carrier communication system
US7755924B2 (en) 2008-01-04 2010-07-13 Texas Instruments Incorporated SRAM employing a read-enabling capacitance
JP2009271966A (ja) * 2008-05-01 2009-11-19 Renesas Technology Corp 不揮発性半導体記憶装置
US8467263B2 (en) * 2010-06-25 2013-06-18 Intel Corporation Memory write operation methods and circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241058A (ja) * 2003-02-07 2004-08-26 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2008021371A (ja) * 2006-07-13 2008-01-31 Renesas Technology Corp 半導体回路
US20080316836A1 (en) * 2007-06-22 2008-12-25 Tan Soon Hwei Ground biased bitline register file

Also Published As

Publication number Publication date
WO2011163022A3 (fr) 2012-03-01
WO2011163022A2 (fr) 2011-12-29
TW201212041A (en) 2012-03-16
JP5642269B2 (ja) 2014-12-17
CN102959633A (zh) 2013-03-06
EP2586029A4 (fr) 2014-04-30
CN102959633B (zh) 2016-11-09
EP2586029B1 (fr) 2020-05-06
US8467263B2 (en) 2013-06-18
EP2586029A2 (fr) 2013-05-01
TWI489484B (zh) 2015-06-21
US20110317508A1 (en) 2011-12-29
JP2013528891A (ja) 2013-07-11
CN202275603U (zh) 2012-06-13
KR20130038883A (ko) 2013-04-18

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