KR101510687B1 - 반도체 장치 및 그 제작 방법 - Google Patents

반도체 장치 및 그 제작 방법 Download PDF

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Publication number
KR101510687B1
KR101510687B1 KR20080060103A KR20080060103A KR101510687B1 KR 101510687 B1 KR101510687 B1 KR 101510687B1 KR 20080060103 A KR20080060103 A KR 20080060103A KR 20080060103 A KR20080060103 A KR 20080060103A KR 101510687 B1 KR101510687 B1 KR 101510687B1
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South Korea
Prior art keywords
layer
single crystal
substrate
crystal semiconductor
semiconductor layer
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Expired - Fee Related
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KR20080060103A
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English (en)
Korean (ko)
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KR20090004549A (ko
Inventor
요시푸미 타나다
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
KR20080060103A 2007-06-29 2008-06-25 반도체 장치 및 그 제작 방법 Expired - Fee Related KR101510687B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007173452 2007-06-29
JPJP-P-2007-00173452 2007-06-29

Publications (2)

Publication Number Publication Date
KR20090004549A KR20090004549A (ko) 2009-01-12
KR101510687B1 true KR101510687B1 (ko) 2015-04-10

Family

ID=39791344

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20080060103A Expired - Fee Related KR101510687B1 (ko) 2007-06-29 2008-06-25 반도체 장치 및 그 제작 방법

Country Status (4)

Country Link
US (2) US7915684B2 (https=)
EP (1) EP2009694A3 (https=)
JP (1) JP5325477B2 (https=)
KR (1) KR101510687B1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120058106A (ko) * 2010-11-29 2012-06-07 삼성전자주식회사 액정 표시 장치 및 그 제조 방법
TWI699023B (zh) 2014-06-30 2020-07-11 日商半導體能源研究所股份有限公司 發光裝置，模組，及電子裝置
US10516075B2 (en) * 2017-09-11 2019-12-24 Nichia Corporation Method of manufacturing a light emitting element
WO2021090106A1 (ja) * 2019-11-08 2021-05-14 株式会社半導体エネルギー研究所 トランジスタ、および電子機器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145438A (ja) * 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2002329868A (ja) * 2001-04-27 2002-11-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2004281878A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体基板の製造方法及びこれにより製造される半導体基板、電気光学装置並びに電子機器
KR20060012549A (ko) * 1999-12-15 2006-02-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｅｌ 디스플레이 장치

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KR0143873B1 (ko) * 1993-02-19 1998-08-17 순페이 야마자끼 절연막 및 반도체장치 및 반도체 장치 제조방법
JPH09116167A (ja) * 1994-12-27 1997-05-02 Seiko Epson Corp 薄膜半導体装置、液晶表示装置及びその製造方法、並びに電子機器
JP3372158B2 (ja) 1996-02-09 2003-01-27 株式会社東芝 半導体装置及びその製造方法
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US6420758B1 (en) * 1998-11-17 2002-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an impurity region overlapping a gate electrode
SG143975A1 (en) 2001-02-28 2008-07-29 Semiconductor Energy Lab Method of manufacturing a semiconductor device
JP3913534B2 (ja) * 2001-11-30 2007-05-09 株式会社半導体エネルギー研究所 表示装置及びこれを用いた表示システム
WO2003105204A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
KR100483049B1 (ko) * 2003-06-03 2005-04-15 삼성전기주식회사 수직구조 질화갈륨계 발광다이오드의 제조방법
US6852652B1 (en) * 2003-09-29 2005-02-08 Sharp Laboratories Of America, Inc. Method of making relaxed silicon-germanium on glass via layer transfer
EP1782474B1 (en) * 2004-08-18 2013-11-27 Corning Incorporated High strain glass/glass-ceramic containing semiconductor-on-insulator structures
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
JP4942341B2 (ja) * 2004-12-24 2012-05-30 三洋電機株式会社 表示装置
US7470573B2 (en) * 2005-02-18 2008-12-30 Sharp Laboratories Of America, Inc. Method of making CMOS devices on strained silicon on glass
JP2006324426A (ja) * 2005-05-18 2006-11-30 Sony Corp 半導体装置およびその製造方法
JP2007173452A (ja) 2005-12-21 2007-07-05 Matsushita Electric Ind Co Ltd バイポーラトランジスタおよびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145438A (ja) * 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
KR20060012549A (ko) * 1999-12-15 2006-02-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｅｌ 디스플레이 장치
JP2002329868A (ja) * 2001-04-27 2002-11-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2004281878A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体基板の製造方法及びこれにより製造される半導体基板、電気光学装置並びに電子機器

Also Published As

Publication number Publication date
KR20090004549A (ko) 2009-01-12
JP5325477B2 (ja) 2013-10-23
EP2009694A3 (en) 2017-06-21
JP2009033144A (ja) 2009-02-12
US20110129987A1 (en) 2011-06-02
US20090002589A1 (en) 2009-01-01
US7915684B2 (en) 2011-03-29
EP2009694A2 (en) 2008-12-31
US8324077B2 (en) 2012-12-04

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