KR101328208B1 - 클락 및 파워 그리드 표준 셀을 사용한 asic 설계 - Google Patents
클락 및 파워 그리드 표준 셀을 사용한 asic 설계 Download PDFInfo
- Publication number
- KR101328208B1 KR101328208B1 KR1020087017299A KR20087017299A KR101328208B1 KR 101328208 B1 KR101328208 B1 KR 101328208B1 KR 1020087017299 A KR1020087017299 A KR 1020087017299A KR 20087017299 A KR20087017299 A KR 20087017299A KR 101328208 B1 KR101328208 B1 KR 101328208B1
- Authority
- KR
- South Korea
- Prior art keywords
- grid
- clock
- power
- design
- directions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/322,160 | 2005-12-29 | ||
| US11/322,160 US7761831B2 (en) | 2005-12-29 | 2005-12-29 | ASIC design using clock and power grid standard cell |
| PCT/CA2006/002118 WO2007073599A1 (en) | 2005-12-29 | 2006-12-22 | Asic design using clock and power grid standard cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20080089597A KR20080089597A (ko) | 2008-10-07 |
| KR101328208B1 true KR101328208B1 (ko) | 2013-11-14 |
Family
ID=38217649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087017299A Expired - Fee Related KR101328208B1 (ko) | 2005-12-29 | 2006-12-22 | 클락 및 파워 그리드 표준 셀을 사용한 asic 설계 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7761831B2 (https=) |
| EP (1) | EP1974382A4 (https=) |
| JP (1) | JP5171639B2 (https=) |
| KR (1) | KR101328208B1 (https=) |
| CN (1) | CN101351886B (https=) |
| TW (1) | TWI444841B (https=) |
| WO (1) | WO2007073599A1 (https=) |
Families Citing this family (57)
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| US7475374B1 (en) * | 2005-12-20 | 2009-01-06 | Advanced Micro Devices, Inc. | Clock grid driven by virtual leaf drivers |
| US7550820B2 (en) * | 2006-08-10 | 2009-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reverse-biased PN diode decoupling capacitor |
| JP4733059B2 (ja) * | 2007-01-30 | 2011-07-27 | 富士通株式会社 | 集積回路設計装置、集積回路設計方法及び集積回路設計プログラム |
| JP2008218730A (ja) * | 2007-03-05 | 2008-09-18 | Nec Electronics Corp | 半導体装置の設計方法及び設計プログラム |
| US20080256380A1 (en) * | 2007-04-16 | 2008-10-16 | Masanori Tsutsumi | Semiconductor integrated circuit and layout method for the same |
| JP2008311361A (ja) | 2007-06-13 | 2008-12-25 | Nec Electronics Corp | 半導体集積回路、半導体集積回路のレイアウト設計方法、及び半導体集積回路の自動レイアウトプログラム |
| KR101477512B1 (ko) * | 2008-03-18 | 2014-12-31 | 삼성전자주식회사 | 액티브 클럭 쉴딩 구조의 회로 및 이를 포함하는 반도체집적 회로 |
| JP2009231513A (ja) * | 2008-03-21 | 2009-10-08 | Elpida Memory Inc | 半導体装置 |
| TWI361362B (en) * | 2008-03-25 | 2012-04-01 | Realtek Semiconductor Corp | Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof |
| US8024690B2 (en) * | 2008-05-19 | 2011-09-20 | Arm Limited | Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices |
| JP4582195B2 (ja) * | 2008-05-29 | 2010-11-17 | ソニー株式会社 | 表示装置 |
| US7847408B2 (en) * | 2009-01-16 | 2010-12-07 | Oracle America, Inc. | Integrated clock and power distribution |
| US8368226B2 (en) * | 2009-12-23 | 2013-02-05 | Oracle International Corporation | Die power structure |
| US8402418B2 (en) * | 2009-12-31 | 2013-03-19 | Nvidia Corporation | System and process for automatic clock routing in an application specific integrated circuit |
| US8742464B2 (en) | 2011-03-03 | 2014-06-03 | Synopsys, Inc. | Power routing in standard cells |
| US8612914B2 (en) | 2011-03-23 | 2013-12-17 | Synopsys, Inc. | Pin routing in standard cells |
| US8631374B2 (en) | 2011-03-30 | 2014-01-14 | Synopsys, Inc. | Cell architecture for increasing transistor size |
| US8513978B2 (en) * | 2011-03-30 | 2013-08-20 | Synopsys, Inc. | Power routing in standard cell designs |
| CN102799698B (zh) * | 2011-05-26 | 2014-07-23 | 国际商业机器公司 | 一种用于专用集成电路的时钟树规划的方法和系统 |
| JP5112539B2 (ja) * | 2011-06-01 | 2013-01-09 | 株式会社東芝 | 半導体集積回路 |
| US9939883B2 (en) | 2012-12-27 | 2018-04-10 | Nvidia Corporation | Supply-voltage control for device power management |
| US8819610B2 (en) | 2013-01-09 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and layout of an integrated circuit |
| US9602083B2 (en) | 2013-07-03 | 2017-03-21 | Nvidia Corporation | Clock generation circuit that tracks critical path across process, voltage and temperature variation |
| US9766649B2 (en) | 2013-07-22 | 2017-09-19 | Nvidia Corporation | Closed loop dynamic voltage and frequency scaling |
| US10103719B2 (en) | 2013-07-22 | 2018-10-16 | Nvidia Corporation | Integrated voltage regulator with in-built process, temperature and aging compensation |
| US9984191B2 (en) | 2014-08-29 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company | Cell layout and structure |
| CN104732029A (zh) * | 2015-03-27 | 2015-06-24 | 西安华芯半导体有限公司 | 一种低失配时钟输出电路 |
| US9640480B2 (en) * | 2015-05-27 | 2017-05-02 | Qualcomm Incorporated | Cross-couple in multi-height sequential cells for uni-directional M1 |
| CN106777437B (zh) * | 2015-11-24 | 2020-05-19 | 龙芯中科技术有限公司 | 时钟系统的构造方法、装置和时钟系统 |
| CN105550459B (zh) * | 2015-12-29 | 2019-03-19 | 山东海量信息技术研究院 | 一种asic设计时钟网络提取系统 |
| US10157254B2 (en) * | 2015-12-29 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Techniques based on electromigration characteristics of cell interconnect |
| WO2017139241A1 (en) | 2016-02-08 | 2017-08-17 | Chaologix, Inc. | Side channel aware automatic place and route |
| US11189569B2 (en) | 2016-09-23 | 2021-11-30 | Advanced Micro Devices, Inc. | Power grid layout designs for integrated circuits |
| US10366199B2 (en) * | 2017-04-11 | 2019-07-30 | Qualcomm Incorporated | Cell-based power grid (PG) architecture |
| US10186510B2 (en) | 2017-05-01 | 2019-01-22 | Advanced Micro Devices, Inc. | Vertical gate all around library architecture |
| US10304728B2 (en) | 2017-05-01 | 2019-05-28 | Advanced Micro Devices, Inc. | Double spacer immersion lithography triple patterning flow and method |
| US10540470B1 (en) * | 2017-05-03 | 2020-01-21 | Cadence Design Systems, Inc. | Generating a power grid for an integrated circuit |
| CN107424991A (zh) * | 2017-06-19 | 2017-12-01 | 南京中感微电子有限公司 | 一种集成电路及印刷电路板 |
| US10747931B2 (en) | 2017-07-28 | 2020-08-18 | Advanced Micro Devices, Inc. | Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic |
| US10163884B1 (en) | 2017-08-02 | 2018-12-25 | Qualcomm Incorporated | Cell architecture with intrinsic decoupling capacitor |
| CN107817870A (zh) * | 2017-10-16 | 2018-03-20 | 算丰科技(北京)有限公司 | 时钟信号传递方法和装置、时钟树、芯片、电子设备 |
| US11120190B2 (en) * | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| US10438937B1 (en) | 2018-04-27 | 2019-10-08 | Advanced Micro Devices, Inc. | Metal zero contact via redundancy on output nodes and inset power rail architecture |
| US10818762B2 (en) | 2018-05-25 | 2020-10-27 | Advanced Micro Devices, Inc. | Gate contact over active region in cell |
| KR102704908B1 (ko) * | 2019-01-24 | 2024-09-09 | 삼성전자주식회사 | 멀티-하이트 스탠다드 셀을 포함하는 집적 회로 및 그 설계 방법 |
| KR102157355B1 (ko) | 2019-04-23 | 2020-09-18 | 삼성전자 주식회사 | 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템 |
| US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
| KR102868559B1 (ko) * | 2020-02-04 | 2025-10-10 | 삼성전자주식회사 | 파워 게이팅 스위치들을 포함하는 반도체 장치 |
| US11687778B2 (en) | 2020-01-06 | 2023-06-27 | The Research Foundation For The State University Of New York | Fakecatcher: detection of synthetic portrait videos using biological signals |
| CN111934684B (zh) * | 2020-07-31 | 2022-12-20 | 新华三半导体技术有限公司 | 一种缓冲器、时钟网格电路和信号驱动方法 |
| KR20230015305A (ko) | 2021-07-20 | 2023-01-31 | 창신 메모리 테크놀로지즈 아이엔씨 | 클록 회로, 메모리 및 반도체 구조의 제조 방법 |
| CN113657065B (zh) * | 2021-07-20 | 2023-08-25 | 长鑫存储技术有限公司 | 时钟电路、存储器及半导体结构的制作方法 |
| US11853672B2 (en) | 2021-07-28 | 2023-12-26 | International Business Machines Corporation | Integrated circuit development using adaptive tile design approach for metal insulator metal capacitor insertion |
| US12205897B2 (en) | 2021-09-23 | 2025-01-21 | Advanced Micro Devices, Inc. | Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells |
| US12308370B2 (en) | 2021-09-29 | 2025-05-20 | Advanced Micro Devices, Inc. | Cross field effect transistors (XFETs) in integrated circuits |
| US11862640B2 (en) | 2021-09-29 | 2024-01-02 | Advanced Micro Devices, Inc. | Cross field effect transistor (XFET) library architecture power routing |
| EP4557365A1 (en) * | 2023-11-15 | 2025-05-21 | Imec VZW | Integrated circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030062949A1 (en) | 2001-09-28 | 2003-04-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device with clock distribution configuration therein |
| US6617621B1 (en) | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
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| US5691662A (en) * | 1994-04-07 | 1997-11-25 | Hitachi Microsystems, Inc. | Method for minimizing clock skew in integrated circuits and printed circuits |
| JPH10189746A (ja) | 1996-12-27 | 1998-07-21 | Oki Electric Ind Co Ltd | Lsi論理回路の配線レイアウト方法 |
| US6205571B1 (en) * | 1998-12-29 | 2001-03-20 | International Business Machines Corporation | X-Y grid tree tuning method |
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| US6397375B1 (en) | 2000-02-18 | 2002-05-28 | Hewlett-Packard Company | Method for managing metal resources for over-the-block routing in integrated circuits |
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| JP2005268278A (ja) * | 2004-03-16 | 2005-09-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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-
2005
- 2005-12-29 US US11/322,160 patent/US7761831B2/en active Active
-
2006
- 2006-12-20 TW TW095147967A patent/TWI444841B/zh not_active IP Right Cessation
- 2006-12-22 EP EP06840545A patent/EP1974382A4/en not_active Withdrawn
- 2006-12-22 JP JP2008547813A patent/JP5171639B2/ja not_active Expired - Fee Related
- 2006-12-22 KR KR1020087017299A patent/KR101328208B1/ko not_active Expired - Fee Related
- 2006-12-22 WO PCT/CA2006/002118 patent/WO2007073599A1/en not_active Ceased
- 2006-12-22 CN CN2006800499085A patent/CN101351886B/zh not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6617621B1 (en) | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
| US20030062949A1 (en) | 2001-09-28 | 2003-04-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device with clock distribution configuration therein |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009521811A (ja) | 2009-06-04 |
| WO2007073599A1 (en) | 2007-07-05 |
| EP1974382A1 (en) | 2008-10-01 |
| JP5171639B2 (ja) | 2013-03-27 |
| CN101351886B (zh) | 2012-05-09 |
| TW200809560A (en) | 2008-02-16 |
| US7761831B2 (en) | 2010-07-20 |
| KR20080089597A (ko) | 2008-10-07 |
| US20070157144A1 (en) | 2007-07-05 |
| TWI444841B (zh) | 2014-07-11 |
| EP1974382A4 (en) | 2010-11-03 |
| CN101351886A (zh) | 2009-01-21 |
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