TWI444841B - 使用時脈和電源柵格標準元件的ａｓｉｃ設計 - Google Patents

使用時脈和電源柵格標準元件的ａｓｉｃ設計 Download PDF

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Publication number
TWI444841B
TWI444841B TW095147967A TW95147967A TWI444841B TW I444841 B TWI444841 B TW I444841B TW 095147967 A TW095147967 A TW 095147967A TW 95147967 A TW95147967 A TW 95147967A TW I444841 B TWI444841 B TW I444841B
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TW
Taiwan
Prior art keywords
grid
clock
design
power
circuit
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Application number
TW095147967A
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English (en)
Chinese (zh)
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TW200809560A (en
Inventor
梅 湯尼
米勒 布魯斯
柯爾曼 蘇珊
派克 西納
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摩賽德科技股份有限公司
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Publication of TW200809560A publication Critical patent/TW200809560A/zh
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Publication of TWI444841B publication Critical patent/TWI444841B/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
TW095147967A 2005-12-29 2006-12-20 使用時脈和電源柵格標準元件的ａｓｉｃ設計 TWI444841B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/322,160 US7761831B2 (en) 2005-12-29 2005-12-29 ASIC design using clock and power grid standard cell

Publications (2)

Publication Number Publication Date
TW200809560A TW200809560A (en) 2008-02-16
TWI444841B true TWI444841B (zh) 2014-07-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147967A TWI444841B (zh) 2005-12-29 2006-12-20 使用時脈和電源柵格標準元件的ａｓｉｃ設計

Country Status (7)

Country Link
US (1) US7761831B2 (https=)
EP (1) EP1974382A4 (https=)
JP (1) JP5171639B2 (https=)
KR (1) KR101328208B1 (https=)
CN (1) CN101351886B (https=)
TW (1) TWI444841B (https=)
WO (1) WO2007073599A1 (https=)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7475374B1 (en) * 2005-12-20 2009-01-06 Advanced Micro Devices, Inc. Clock grid driven by virtual leaf drivers
US7550820B2 (en) * 2006-08-10 2009-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse-biased PN diode decoupling capacitor
JP4733059B2 (ja) * 2007-01-30 2011-07-27 富士通株式会社 集積回路設計装置、集積回路設計方法及び集積回路設計プログラム
JP2008218730A (ja) * 2007-03-05 2008-09-18 Nec Electronics Corp 半導体装置の設計方法及び設計プログラム
US20080256380A1 (en) * 2007-04-16 2008-10-16 Masanori Tsutsumi Semiconductor integrated circuit and layout method for the same
JP2008311361A (ja) 2007-06-13 2008-12-25 Nec Electronics Corp 半導体集積回路、半導体集積回路のレイアウト設計方法、及び半導体集積回路の自動レイアウトプログラム
KR101477512B1 (ko) * 2008-03-18 2014-12-31 삼성전자주식회사 액티브 클럭 쉴딩 구조의 회로 및 이를 포함하는 반도체집적 회로
JP2009231513A (ja) * 2008-03-21 2009-10-08 Elpida Memory Inc 半導体装置
TWI361362B (en) * 2008-03-25 2012-04-01 Realtek Semiconductor Corp Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof
US8024690B2 (en) * 2008-05-19 2011-09-20 Arm Limited Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices
JP4582195B2 (ja) * 2008-05-29 2010-11-17 ソニー株式会社 表示装置
US7847408B2 (en) * 2009-01-16 2010-12-07 Oracle America, Inc. Integrated clock and power distribution
US8368226B2 (en) * 2009-12-23 2013-02-05 Oracle International Corporation Die power structure
US8402418B2 (en) * 2009-12-31 2013-03-19 Nvidia Corporation System and process for automatic clock routing in an application specific integrated circuit
US8742464B2 (en) 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8612914B2 (en) 2011-03-23 2013-12-17 Synopsys, Inc. Pin routing in standard cells
US8631374B2 (en) 2011-03-30 2014-01-14 Synopsys, Inc. Cell architecture for increasing transistor size
US8513978B2 (en) * 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
CN102799698B (zh) * 2011-05-26 2014-07-23 国际商业机器公司 一种用于专用集成电路的时钟树规划的方法和系统
JP5112539B2 (ja) * 2011-06-01 2013-01-09 株式会社東芝 半導体集積回路
US9939883B2 (en) 2012-12-27 2018-04-10 Nvidia Corporation Supply-voltage control for device power management
US8819610B2 (en) 2013-01-09 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
US9602083B2 (en) 2013-07-03 2017-03-21 Nvidia Corporation Clock generation circuit that tracks critical path across process, voltage and temperature variation
US9766649B2 (en) 2013-07-22 2017-09-19 Nvidia Corporation Closed loop dynamic voltage and frequency scaling
US10103719B2 (en) 2013-07-22 2018-10-16 Nvidia Corporation Integrated voltage regulator with in-built process, temperature and aging compensation
US9984191B2 (en) 2014-08-29 2018-05-29 Taiwan Semiconductor Manufacturing Company Cell layout and structure
CN104732029A (zh) * 2015-03-27 2015-06-24 西安华芯半导体有限公司 一种低失配时钟输出电路
US9640480B2 (en) * 2015-05-27 2017-05-02 Qualcomm Incorporated Cross-couple in multi-height sequential cells for uni-directional M1
CN106777437B (zh) * 2015-11-24 2020-05-19 龙芯中科技术有限公司 时钟系统的构造方法、装置和时钟系统
CN105550459B (zh) * 2015-12-29 2019-03-19 山东海量信息技术研究院 一种asic设计时钟网络提取系统
US10157254B2 (en) * 2015-12-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Techniques based on electromigration characteristics of cell interconnect
WO2017139241A1 (en) 2016-02-08 2017-08-17 Chaologix, Inc. Side channel aware automatic place and route
US11189569B2 (en) 2016-09-23 2021-11-30 Advanced Micro Devices, Inc. Power grid layout designs for integrated circuits
US10366199B2 (en) * 2017-04-11 2019-07-30 Qualcomm Incorporated Cell-based power grid (PG) architecture
US10186510B2 (en) 2017-05-01 2019-01-22 Advanced Micro Devices, Inc. Vertical gate all around library architecture
US10304728B2 (en) 2017-05-01 2019-05-28 Advanced Micro Devices, Inc. Double spacer immersion lithography triple patterning flow and method
US10540470B1 (en) * 2017-05-03 2020-01-21 Cadence Design Systems, Inc. Generating a power grid for an integrated circuit
CN107424991A (zh) * 2017-06-19 2017-12-01 南京中感微电子有限公司 一种集成电路及印刷电路板
US10747931B2 (en) 2017-07-28 2020-08-18 Advanced Micro Devices, Inc. Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic
US10163884B1 (en) 2017-08-02 2018-12-25 Qualcomm Incorporated Cell architecture with intrinsic decoupling capacitor
CN107817870A (zh) * 2017-10-16 2018-03-20 算丰科技（北京）有限公司 时钟信号传递方法和装置、时钟树、芯片、电子设备
US11120190B2 (en) * 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
US10438937B1 (en) 2018-04-27 2019-10-08 Advanced Micro Devices, Inc. Metal zero contact via redundancy on output nodes and inset power rail architecture
US10818762B2 (en) 2018-05-25 2020-10-27 Advanced Micro Devices, Inc. Gate contact over active region in cell
KR102704908B1 (ko) * 2019-01-24 2024-09-09 삼성전자주식회사 멀티-하이트 스탠다드 셀을 포함하는 집적 회로 및 그 설계 방법
KR102157355B1 (ko) 2019-04-23 2020-09-18 삼성전자 주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
US10796061B1 (en) 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
KR102868559B1 (ko) * 2020-02-04 2025-10-10 삼성전자주식회사 파워 게이팅 스위치들을 포함하는 반도체 장치
US11687778B2 (en) 2020-01-06 2023-06-27 The Research Foundation For The State University Of New York Fakecatcher: detection of synthetic portrait videos using biological signals
CN111934684B (zh) * 2020-07-31 2022-12-20 新华三半导体技术有限公司 一种缓冲器、时钟网格电路和信号驱动方法
KR20230015305A (ko) 2021-07-20 2023-01-31 창신 메모리 테크놀로지즈 아이엔씨 클록 회로, 메모리 및 반도체 구조의 제조 방법
CN113657065B (zh) * 2021-07-20 2023-08-25 长鑫存储技术有限公司 时钟电路、存储器及半导体结构的制作方法
US11853672B2 (en) 2021-07-28 2023-12-26 International Business Machines Corporation Integrated circuit development using adaptive tile design approach for metal insulator metal capacitor insertion
US12205897B2 (en) 2021-09-23 2025-01-21 Advanced Micro Devices, Inc. Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells
US12308370B2 (en) 2021-09-29 2025-05-20 Advanced Micro Devices, Inc. Cross field effect transistors (XFETs) in integrated circuits
US11862640B2 (en) 2021-09-29 2024-01-02 Advanced Micro Devices, Inc. Cross field effect transistor (XFET) library architecture power routing
EP4557365A1 (en) * 2023-11-15 2025-05-21 Imec VZW Integrated circuit device

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691662A (en) * 1994-04-07 1997-11-25 Hitachi Microsystems, Inc. Method for minimizing clock skew in integrated circuits and printed circuits
JPH10189746A (ja) 1996-12-27 1998-07-21 Oki Electric Ind Co Ltd Ｌｓｉ論理回路の配線レイアウト方法
US6205571B1 (en) * 1998-12-29 2001-03-20 International Business Machines Corporation X-Y grid tree tuning method
US6510545B1 (en) * 2000-01-19 2003-01-21 Sun Microsystems, Inc. Automated shielding algorithm for dynamic circuits
US6397375B1 (en) 2000-02-18 2002-05-28 Hewlett-Packard Company Method for managing metal resources for over-the-block routing in integrated circuits
US6467074B1 (en) * 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks
US6370678B1 (en) * 2000-04-27 2002-04-09 Agilent Technologies, Inc. System and method for adjusting logic synthesis based on power supply circuit models
US6617621B1 (en) * 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
US6737728B1 (en) * 2000-10-12 2004-05-18 Intel Corporation On-chip decoupling capacitor and method of making same
JP2002158335A (ja) * 2000-11-22 2002-05-31 Toshiba Corp 半導体装置の配線構造およびその設計方法
US6522186B2 (en) 2001-06-27 2003-02-18 Intel Corporation Hierarchical clock grid for on-die salphasic clocking
US6909127B2 (en) 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
US6614279B2 (en) * 2001-08-29 2003-09-02 Intel Corporation Clock receiver circuit for on-die salphasic clocking
US6823499B1 (en) * 2001-09-18 2004-11-23 Lsi Logic Corporation Method for designing application specific integrated circuit structure
JP4931308B2 (ja) * 2001-09-28 2012-05-16 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US6910194B2 (en) * 2002-07-19 2005-06-21 Agilent Technologies, Inc. Systems and methods for timing a linear data path element during signal-timing verification of an integrated circuit design
US7739624B2 (en) * 2002-07-29 2010-06-15 Synopsys, Inc. Methods and apparatuses to generate a shielding mesh for integrated circuit devices
US6898769B2 (en) * 2002-10-10 2005-05-24 International Business Machines Corporation Decoupling capacitor sizing and placement
US6948142B2 (en) * 2003-06-02 2005-09-20 Lsi Logic Corporation Intelligent engine for protection against injected crosstalk delay
US7107200B1 (en) * 2003-10-03 2006-09-12 Sun Microsystems, Inc. Method and apparatus for predicting clock skew for incomplete integrated circuit design
US7111266B2 (en) * 2003-11-24 2006-09-19 International Business Machines Corp. Multiple voltage integrated circuit and design method therefor
US7237217B2 (en) * 2003-11-24 2007-06-26 International Business Machines Corporation Resonant tree driven clock distribution grid
US7117457B2 (en) * 2003-12-17 2006-10-03 Sequence Design, Inc. Current scheduling system and method for optimizing multi-threshold CMOS designs
JP2005268278A (ja) * 2004-03-16 2005-09-29 Matsushita Electric Ind Co Ltd 半導体装置
US7424696B2 (en) * 2004-12-03 2008-09-09 Lsi Corporation Power mesh for multiple frequency operation of semiconductor products
US7788613B2 (en) * 2005-07-06 2010-08-31 Fujitsu Limited Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture

Also Published As

Publication number Publication date
KR101328208B1 (ko) 2013-11-14
JP2009521811A (ja) 2009-06-04
WO2007073599A1 (en) 2007-07-05
EP1974382A1 (en) 2008-10-01
JP5171639B2 (ja) 2013-03-27
CN101351886B (zh) 2012-05-09
TW200809560A (en) 2008-02-16
US7761831B2 (en) 2010-07-20
KR20080089597A (ko) 2008-10-07
US20070157144A1 (en) 2007-07-05
EP1974382A4 (en) 2010-11-03
CN101351886A (zh) 2009-01-21

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