Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/10—Distribution of clock signals, e.g. skew
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/90—Masterslice integrated circuits
  • H10D84/903—Masterslice integrated circuits comprising field effect technology
  • H10D84/907—CMOS gate arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts

Definitions

• An Application-Specific Integrated Circuit is an integrated circuit custom designed for a particular use, also referred to as a System on Chip (SoC).
• SoC System on Chip
• a few examples of ASIC implementations may be found in cellular phones, automotive computers, and personal data assistants (PDAs). The mentioned examples have limited functionality and are therefore used to perform specific tasks.
• a contrasting example to the ASIC design is a microprocessor. Microprocessors are designed to adapt to many purposes. The first phase of an ASIC design typically begins with a team of design engineers who determine the functional requirements of the ASIC to be built. Once the required functions have been determined, the design team then constructs a description of the ASIC using a hardware description language (HDL).
• HDL hardware description language
• RTL Register Transfer Level
• HDL is used to describe the circuit's operation, its design, and tests to verify its operation by means of simulation.
• a logic synthesis tool such as Design Compiler TM by Synopsys, may then be used to transform the RTL design into a large collection of lower-level constructs called standard cells.
• Standard cells are the basic building blocks of ASICs. Standard cells, typically taken from a library, consist of pre-characterized collections of gates. The standard cells used in the ASIC design are specific to the intended function of the ASIC design. The resulting collection of standard cells and a power grid, providing the necessary electrical connections, is called a gate-level netlist. The gate-level netlist is processed by a placement tool, which one-by-one places the individual standard cells onto a designated region within the power grid. Standard cells use a variable number of metal layers for local routing within the cell depending on the complexity of the cell design. The placement of the standard cells is subject to a variety of specified constraints. Therefore, a height requirement is typically set upon standard cells such that all standard cells have a height equal to the required height or a multiple thereof.
• a routing tool forms the electrical connections between the standard cells and the power grid. Estimations on delays, clock skew, parasitic resistances and capacitances, and power consumptions are also made and used in a final round of testing. During this round of testing, alterations to the design may be made in order to increase the performance of the device. Once the testing is complete, the design is finally released for chip fabrication.
• An ASIC clock distribution network is characterized by layout area used, clock insertion delay and clock skew.
• Clock skew is a phenomenon seen in synchronous circuits and occurs when a clock signal arrives at different components of the circuit at different times; in other words, when the clock insertion delay from the clock source differs to each component.
• a clock signal is generated by a clock circuit and is distributed throughout the ASIC in a balanced network of clock buffers and metal routing.
• Two general architectures for ASIC clock distribution networks are the Clock Trunk and the Clock Tree, each having physical and electrical characteristics which differ, and depending on the application, one clock architecture may be more beneficial to use in an application than another.
• the clock trunk architecture incorporates a large central conductor or trunk in its design, which is driven from one or both ends, with smaller branch conductors extending perpendicularly out from the trunk to distribute the clock signal to the ASIC components on either side of the trunk. Because the trunk clock distribution network has unequal metal paths from the clock source to the driven components, it is inherently unbalanced and introduces a small amount of clock skew in the clock distribution due to differing RC delays in the metal paths to each component.
• Figure 1 displays an example of a clock trunk structure 150.
• the 150 includes a central conductor 110, comprising smaller branch conductors 113 extending perpendicularly out from the central conductor to distribute the clock signal 112 to the ASIC components on either side of the conductor.
• the clock signal CLK 112 is initially passed through a buffer 116 resulting in a clock signal CLK' 117.
• Signal CLK' 117 is passed through both sides of the conductor 110 through buffers 115 and 111.
• Buffer 111 is an optional buffer used to minimize clock skew.
• the tree architecture is a balanced clock distribution scheme, having equal paths from the clock source to the components by design.
• the tree architecture uses a central distribution point, symmetrical branching, buffering and sub-branching to distribute clocks to components.
• a clock tree may also have a root and a trunk to convey the clock source to the first branching point.
• the metal conductors in each branch of a clock tree are usually so closely matched as to introduce negligible clock skew into the clock distribution network on their own.
• all of the clock buffers within the network must have closely matched characteristics and the loads presented to these buffers must be balanced.
• the branched symmetry of clock trees makes them practical to be generated automatically by ASIC tools. Although quick to generate a complete clock network conforming to worst-case skew margins, a major failing of these ASIC tools, is to minimize the clock skew to levels attainable in custom clock tree designs.
• Figure IA displays a simplified row-based cell layout 100 featuring an embedded clock tree 107.
• Cell layout 100 comprises two power supply rails VDD 101 and VSS 103, forming a power grid.
• Standard cells 105 are placed in the power grid between the voltage supply rails 101 and 103.
• a clock circuit 109 generates a clock signal which is sent to destinations, or nodes, 111, 113, 115 and 117 of the clock tree 107.
• a clock signal, originating from clock circuit 109 should have the same distance to travel to node 113 as it does to nodes 1 11, 115, and 117. If the time taken for the clock signal to reach node 113 is greater or less than the time taken to reach nodes 111, 115, or 117, a clock skew is present. The greater the deviation of the time difference reaching each node, the greater the clock skew.
• FIG. 2A A more detailed view of a clock tree may be seen in Figure 2A.
• An H-clock tree 200 is typically used in ASIC designs.
• Clock tree 200 comprises four leaves, or nodes, 201, 202, 203, and 204.
• the clock tree 200 is built using a series of metal wires 210 and buffers 211.
• a clock signal elk is sent through the tree, resulting in a signal elk' in node 202 and a signal elk" in node 204.
• the timing diagram of Figure 2B graphically depicts clock signals elk, elk' and elk". As may be seen from the timing diagram, the insertion delays of the rising edges of signals elk' and elk" are significantly different, causing a skew. Such a difference needs to be addressed in the timing budget of the design.
• a circuit is formed from a plurality of design cells.
• the design cells comprise grid cells that together form a clock grid, having rails in first and second orientations and circuit cells forming circuits within and coupled to the clock.
• the grid cells may also be used to form a power grid, where the power grid may provide a decoupling capacitance between power and ground lines in each grid cell.
• the power grid may also provide a shielding for the clock grid.
• Each grid cell may further comprise at least one power rail and at least one clock line in the same metal layer. The at least one power rail and at least one clock line may be in one of the first and second orientations.
• Grid cells There may be multiple types of grid cells. Those providing power and clock lines in respective orientations and those proving and interconnecting rails of different orientations.
• One type of grid cell may comprise at least one power rail and at least one clock line, in a first orientation.
• Another type may comprise at least one power rail and at least one clock line in a second orientation and at least one other power rail in a first orientation.
• a third type of grid cell may comprise at least one power rail and at least one clock line in each of the first and second orientations.
• the third grid cell type may also interconnect the power rails of different orientation and clock lines of different orientation.
• a method of forming the circuit comprises designing a clock grid of individual grid cells and designing a circuit of individual standard cells within and coupled to the clock grid.
• the method may also provide an integrated power and clock grid.
• the method may comprise placing individual grid cells with an ASIC tool, where the grid cells comprise power and clock elements, and placing individual standard cells with the ASIC tool, the ASIC tool being a software tool.
• a design system may also be formed.
• the design system comprises at least one standard cell, a plurality of grid unit cells, placing software that places the plurality of grid unit cells and the at least one standard cell, and routing software.
• the routing software provides interconnections between the plurality of grid unit cells; between the at least one standard cell and the plurality of grid unit cells; and between the at least one standard cell and at least one other standard cell.
• the design system may also comprise first orientation cell means for providing clock and power lines in a first orientation, second orientation cell means for providing clock and power lines in a second orientation, and interconnection cell means for providing and interconnecting clock and power lines in a first orientation and clock and power lines in a second orientation.
• the integration of the power and clock grids reduce clock skew in an application which is easily implemented by ASIC tools, and also provides the necessary decoupling and shielding without adding additional devices to the ASIC design.
• the integrated clock and power grid is also capable of being fabricated on fewer metal layers, thus greatly lowering the complexity of the ASIC design.
• FIG. 1 is a schematic of a clock trunk
• FIG. IA displays a simplified row-based cell layout
• FIG. 2A is a schematic of a clock tree and FIG. 2B is a timing diagram representing the skew of the clock tree;
• FIG. 3A is a schematic of a clock grid and FIG. 3B is a timing diagram representing the skew of the clock grid;
• FIG. 4 depicts an implementation of a grid system incorporating horizontal, vertical and corner grid unit cells
• FIG. 5 is a flow chart describing grid design steps
• FIG. 6 is a plan view of a horizontal grid unit cell
• FIG. 7A depicts a cross-sectional view of a PMOS horizontal grid unit cell of
• FIG. 6 is a diagrammatic representation of FIG. 6
• FIG. 7B depicts a cross-sectional view of an NMOS horizontal grid unit cell of FIG. 6;
• FIG. 8 shows a perspective view of the horizontal grid unit cell of FIG. 6;
• FIG. 9 shows a plan view of a vertical grid unit cell;
• FIG. 10 is a perspective view of the vertical grid unit cell of FIG. 9;
• FIG. 11 shows a plan view of a corner grid unit cell
• FIG. 12 shows a perspective view of the corner grid unit cell of FIG. 11.
• nodes 201-204 In order to achieve minimum skew in an H-clock tree, as shown in Figure 2, nodes 201-204 must be balanced. Since each node 201-204 will see a different load, balancing the nodes becomes a difficult task.
• the clock grid architecture is characterized by an orthogonal array of interconnected wires driven by a plurality of matched clock buffers placed at regular intervals along the grid.
• the clock grid forms a single low-skew clock network, which obviates any need for balancing loads.
• the grid In layout, the grid must be extended to cover all clocked components in the ASIC design.
• ASIC clock grids are usually custom designs, which must be merged into the place-and-rout area of the design. No commercially available ASIC tools exist today to generate clock grids automatically. By subdividing a custom clock grid into cell-sized units and making these units compatible with Standard Cell Libraries, the inventors believe that automatic clock grid generation would be feasible and practical for ASICs. Thought automatic clock grid generation capability be absent from current ASIC tool-sets, the inventors believe that Standard Cell based clock grid cells are beneficial, can be easily be placed into a layout with Standard Cells and fit seamlessly into existing ASIC design flows to yield high-performance clock distribution.
• FIG. 3A shows a clock grid 300 comprised of a conduction grid 301 and buffers 21 1.
• the clock grid 300 of Figure 3A comprises one common node, i.e., the conduction grid 301. Therefore, once a clock signal elk is transmitted to the clock grid 300, the different portions of the clock grid 300 will receive the signals elk' and elk" at approximately the same time since there is only one common node. The different clock signals received on the clock grid will also rise and fall at approximately the same time, as may be seen in the timing diagram of Figure 3B. Therefore, using a clock grid system, minimum clock skew may be achieved. Note that the metal conductors forming the conduction grid have low but finite resistance. Depending on the configuration of the clock grid and the load capacitance, a small RC- based clock skew will exist between different parts of the conduction grid.
• the placement and routing tools are not designed to incorporate clock grids and therefore do not have the capacity to include them in the ASIC design. That is, the placement and routing tools are configured to place the standard cells and to route interconnections between the standard cells placed.
• a power and clock design disclosed here allows for minimum clock skew and is also compatible with various ASIC designs tools.
• An integrated power and clock grid comprising grid unit cells is presented and shown in Figure 4.
• the integrated clock and power grid 400 is comprised of a plurality of grid unit cells which serve as the building blocks of the integrated power and clock grid 400.
• the grid unit cells are placeable one-by-one and may be tiled together to form the integrated power and clock grid 400.
• the grid unit cells may be handled and placed by the ASIC placement and routing tools just in a similar manner in which these tools are used for the standard cells.
• the integrated power and clock grid 400 is composed of vertical sections 403, horizontal sections 404, and intersections 405 of the vertical and horizontal sections.
• the grid sections 403, 404 and 405 are composed of three different types of grid unit cells. More specifically, the vertical section 403 includes plural vertical grid unit cells 407, the horizontal section 404 includes plural horizontal grid unit cells 409, and intersections 405 includes a corner grid unit cell 411.
• the vertical grid unit cells 407 are used in constructing the vertical sections 403 of the grid 400, while the horizontal grid unit cells 409 constitute the horizontal sections 404 of the grid 400.
• Corner grid unit cells 411 are designed to constitute the intersections 405 between the horizontal and vertical sections 404 and 403, respectively, and therefore serve as an interconnection coupler for the horizontal and vertical grid unit cells 409 and 407, respectively, at the intersections 405.
• the horizontal section 404 of the grid 400 is fabricated by linearly arranging the horizontal grid unit cells 409 in a horizontal direction.
• the vertical section 407 of the grid 400 is fabricated by linearly arranging the vertical grid unit cells 407 in a vertical direction.
• the corner grid unit cell 411 is used at the intersections 405 of the grid 400 in such a way to interconnect the vertical grid unit cells 407 used in the vertical sections 403 of the grid, with the horizontal grid unit cells 409, used in the horizontal sections 404 of the grid.
• the terms “horizontal” and “vertical” are used throughout the description for simplicity, but may include any two different orientations as long as they are substantially perpendicular to each other.
• the vertical grid unit cell 407, the horizontal grid unit cell 409, and the corner grid unit cell 411 will be further explained hereinafter, referring to Figures 6 to 12 which provide simplified topographical views for the respective grid unit cells.
• FIG. 5 is a flow chart 500 showing the steps of designing ASICs comprising the integrated power and clock grid 400 of Figure 4.
• step 501 involves organizing grid unit cells into a desired grid formation using a placement tool.
• Figure 4 shows an illustrative example of how the grid unit cells are placed.
• the next step of forming an integrated power and clock grid is to place standard cells using the placement tool, as illustrated in step 502.
• the placement tool used in steps 501 and 502 may be the conventional ASIC placement tools, or may be especially designed for placing the grid unit cells 407, 409 and 411 and the standard cells.
• the standard cells which provide the logic of the ASIC device to be built, are placed in grid openings 401. Multiple standard cells may be placed in each grid opening.
• electrical interconnections are provided between individual grid unit cells; between individual standard cells and the grid unit cells; and between the various individual standard cells (step 503).
• the electrical interconnections are made using a routing tool, which may be also a conventional ASIC software tool.
• the clock and power grid cells when placed in an ASIC to form a clock and power grid, may interconnect themselves by abutment. In other words, no routing is required by the ASIC place-and-rout tools to interconnect the clock and power grid cells to each other. More specifically, the clock and power grid cell may be configured such that neighboring cells can be electrically connected through abutment with each other by simply placing the grid cells on desired positions in an ASIC layout. However, clocks and power are routed between the grid formed by placement and the standard logic cells contained inside the clock and power grid structure.
• FIG. 6 A plan view of a horizontal grid unit 409 is shown in Figure 6; a cross-sectional views (A-A') are shown in Figures 7A and 7B; and a perspective view is shown in Figure
• Figure 7A depicts a PMOS embodiment while Figure 7B depicts an NMOS embodiment.
• a mos-fet well 601 of a first conductivity is formed in a substrate and two source/drain diffusions formed within the first well 601.
• two n+ diffusions 615 or well taps are formed within well 601.
• Well taps 615 ensure that the well is at a proper electrical potential.
• the well taps 615 serve as the source/drain of the nonfunctional n-channel transistor.
• the PMOS embodiment comprise additional p+ diffusions 603 which serve as the source/drain for the nonfunctional p-channel transistor.
• the p+ and n+ diffusions 603 and 615, respectively, are extended in horizontal direction along the first (608a and 608b) and second (609) horizontal power rails.
• a gate oxide 604 is formed between the source/drain diffusions 615, for the
• the gate oxide 604 is formed between source/drain diffusions 603.
• Gate oxide 604 is covered by a conductive poly- silicon material forming the mos-fet gate 604a.
• a shallow trench isolation 617 is formed on the outer periphery of the device in order to provide electronic isolation.
• First horizontal power rails 608a and 608b are electrically connected to the source/drains 603 by a contact 605 and a second horizontal power rail 609, for example a VSS voltage rail, is electrically connected to the gate 604a by a contact 607.
• the first horizontal power rails 608a and 608b are also electrically connected to the well taps 615 by a contact 619. It should be appreciated that any number of contacts may be used.
• a first horizontal clock line 611 for example sclk
• a second horizontal clock line 610 for example elk
• the horizontal power rails 608 and 609 and the horizontal clock lines 610 and 611 are all fabricated on a first metallization layer Ml .
• the clock lines disposed between the power rails are surrounded and shielded on three sides by a DC signal to reduce electromagnetic interference to nearby signals in the ASIC and to reduce electromagnetic interference from other ASIC signals to the clocks.
• the grid unit cells are structured to provide VDD-VSS decoupling capacitance.
• the decoupling capacitance of the PMOS transistor embodiment will now be discussed in detail.
• the n-well 601, well tap 615, and p+ diffusions 603 form a PMOS transistor structure, as shown in Figure 7A. That is, the p+ diffusions 603 are the source and drain of the transistor. With the gate connected to VSS and the source, drain and n-well to VDD, the p-channel transistor is always held in an on state where the channel material is fully inverted to form a conductor between source and drain.
• the gate 604a constitutes one plate of a capacitor
• the source/drain 603 and formed p-channel constitute the other plate with the gate oxide 604 constituting a dielectric material between the two plates.
• the junction capacitance formed between the n-well 601, which is at VDD potential, and the silicon substrate 600, which is at VSS potential adds significantly to the gate capacitance provided by the PMOS transistor.
• the PMOS transistor provides an effective decoupling capacitance between the power and ground lines in each grid unit cell. Decoupling is an important factor in an ASIC design. Voltages in integrated circuits tend to become unstable if a substantial amount of switching occurs in the circuit.
• FIG. 9 A detailed plan view of a vertical grid unit cell 407 is shown in Figure 9 and a perspective view thereof in Figure 10.
• the vertical grid unit cell 407 includes two first vertical power rails 801a and 801b, for example VDD voltage rails, and a second vertical power rail 802, for example a VSS voltage rail, disposed between the two first vertical power rails 801a and 801b.
• Two vertical clock lines 804 and 806 (for example clocks elk and sclk, respectively) are disposed between the first vertical power rail 801a and 801b, and the second vertical power rail 802.
• clock line elk 804 is situated between first vertical power rail 801a and second vertical power rail 802.
• Clock line sclk 806 is situated between first vertical power rail 801b and second vertical power rail 802.
• the vertical power rails and clock lines are all formed on a second metallization layer M2, which is fabricated on a higher level than the first metallization layer Ml.
• the vertical grid unit cell 407 includes local horizontal VDD and VSS power rails 708 and 709, respectively, in the first metallization layer Ml.
• the vertical power rails and clock lines of the vertical grid unit cell 407 run perpendicularly to the local horizontal VDD and VSS power rails 708 and 709.
• the first vertical power rails 801a and 801b of the second metallization layer M2 is electrically connected to the horizontal local VDD power rails 708a and 708b respectively through a via 901 and the second vertical power rail 802 is electrically connected to the horizontal local VSS power rail 709 through a via 903.
• the local horizontal power rails 708 and 709, and well structures 703 and 701 are, in general, structured in a similar way to that of the horizontal grit unit cell 409, except that it does not include any clock lines.
• the local horizontal power rails and clock lines of the vertical grid unit 407 are of the same height as the horizontal power rails in the horizontal grid unit cell 409, which are all fabricated on the first metallization layer Ml.
• the standard cells also contain logic which are of the same height as the first metallization layer Ml. As such all vertical grid unit cells must comprise voltage elements on the first metallization layer Ml in order to provide power to the various standard cells which will be placed throughout the integrated power and clock grid 400.
• the vertical grid unit cell 407 comprises an n-type well 701 with two p+ source/drain diffusions 703 and two n+ diffusions 715 disposed therein. It should be appreciated that the vertical grid unit cell 407 may also comprise an NMOS transistor configuration. A layer of gate oxide 704 is disposed between the two p+ source/drains 703 and covered by a conductive poly-silicon material forming the mos-fet gate 704a.
• the local horizontal VDD power rails 708a and 708b are fabricated on the first metallization layer Ml and are connected to the p+ diffusions 703 with contacts 705 and are also connected to the n+ diffusions 715 with contacts 706.
• the local horizontal VSS power rail 709 also fabricated on the first metallization layer Ml, is connected to the gate 704a by a contact 707.
• the first vertical power rails 801a and 801b are fabricated on the second metallization layer M2, in a vertical orientation with respect to the local horizontal VDD power rails 708a and 708b, and are electrically connected to the local horizontal VDD power rails 708a and 708b by vias 901.
• the second vertical power rail 802, in a vertical orientation with respect to the local horizontal VSS power rail 709, is also fabricated on the second metallization layer M2 and is electrically connected to the local horizontal VSS power rail 709 by a via 903.
• the vertical clock lines 804 and 806 are fabricated on the second metallization layer M2 and are situated between the first vertical power rails 801a and 801b and the second vertical power rail 802.
• Figure 11 shows a plan view of a corner grid unit cell 411
• Figure 12 shows a perspective view of the corner grid unit cell 411.
• the corner grid unit cell 411 contains power and clock elements in both the horizontal and vertical directions. All of the elements comprising a horizontal orientation are fabricated on the first metal layer Ml and all of the elements comprising a vertical orientation are fabricated on the second metal layer M2.
• Two p+ source/drains 803 and two n+ well taps 815 are diffused into the n-type well 805.
• a gate oxide 807 is deposited between the two p+ source/drains 803 and covered by a conductive poly-silicon material forming the mos-fet gate 807a.
• First horizontal power rails 905a and 905b are fabricated on the first metal layer Ml and are connected to the p+ source/drains 803 through contacts 809 and are also connected to n+ well taps 815 through contacts 810.
• a second horizontal power rail 907 is also fabricated on the first metal layer Ml and is connected to the gate 807a through contact 811.
• Horizontal clock lines 911 and 909 are located on metal layer Ml between power rails 905 and 907. Specifically, clock line 911, sclk, is situated between power rails 905b and 907.
• Clock line 909, elk is situated between power rails 905a and 907.
• First vertical power rails 1001a and 1001b are fabricated on metal layer M2 and are connected to first horizontal power rails 905a and 905b by a via 913.
• a second vertical power rail 1003, for example a VSS voltage rail is also fabricated on the second metal layer M2 and is connected to horizontal power rail 907 by via 915.
• Vertical clock lines 1005, elk, and 1007, sclk are connected to horizontal clock lines 909, elk, and 91 1, sclk, through vias 919 and 917 respectively.
• corner grid unit 411 comprises all of the elements found in both the vertical and horizontal grid units, 407 and 409 respectively, the corner grid unit is therefore able to couple the vertical and horizontal grid unit cells.
• the examples provided thus far have comprised two power VDD rails, one power
• VSS rail and two clock lines sclk and elk. It should be appreciated that other combinations involving a different number of voltage rails and clock lines may be used.
• the integration of the power and clock grids not only reduces clock skew in an application which is easily implemented by ASIC tools, but it also provides decoupling and shielding without adding additional devices to the ASIC design.
• Another advantage of the integrated clock and power grid is that the design is capable of being fabricated on fewer metal layers, thus greatly lowering the complexity of the ASIC design.

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• 2005
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