KR101311332B1 - 임시 반도체 구조 본딩 방법들 및 관련 본딩된 반도체 구조들 - Google Patents

임시 반도체 구조 본딩 방법들 및 관련 본딩된 반도체 구조들 Download PDF

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KR101311332B1
KR101311332B1 KR1020110058448A KR20110058448A KR101311332B1 KR 101311332 B1 KR101311332 B1 KR 101311332B1 KR 1020110058448 A KR1020110058448 A KR 1020110058448A KR 20110058448 A KR20110058448 A KR 20110058448A KR 101311332 B1 KR101311332 B1 KR 101311332B1
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semiconductor structure
semiconductor
wafer
bonded
carrier wafer
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KR1020110058448A
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English (en)
Korean (ko)
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KR20120010120A (ko
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마리암 사다카
이오누트 라두
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소이텍
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Priority claimed from US12/839,203 external-priority patent/US8461017B2/en
Priority claimed from FR1056122A external-priority patent/FR2963162B1/fr
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Publication of KR20120010120A publication Critical patent/KR20120010120A/ko
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2011—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline insulating material, e.g. sapphire
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    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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    • H01L2924/1304—Transistor
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Micromachines (AREA)
KR1020110058448A 2010-07-19 2011-06-16 임시 반도체 구조 본딩 방법들 및 관련 본딩된 반도체 구조들 KR101311332B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/839,203 2010-07-19
US12/839,203 US8461017B2 (en) 2010-07-19 2010-07-19 Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
FR1056122A FR2963162B1 (fr) 2010-07-26 2010-07-26 Procedes de collage de structure semi-conductrice temporaire et structures semi-conductrices collees correspondantes
FR1056122 2010-07-26

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KR20120010120A KR20120010120A (ko) 2012-02-02
KR101311332B1 true KR101311332B1 (ko) 2013-09-27

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KR (1) KR101311332B1 (zh)
CN (2) CN102339769A (zh)
SG (1) SG177817A1 (zh)
TW (1) TWI445101B (zh)

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FR2978605B1 (fr) * 2011-07-28 2015-10-16 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
US9041206B2 (en) 2013-03-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
JP6429388B2 (ja) * 2015-03-19 2018-11-28 株式会社ディスコ 積層デバイスの製造方法
US10867834B2 (en) * 2015-12-31 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN107346746B (zh) * 2016-05-05 2020-09-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US11764198B2 (en) 2017-03-02 2023-09-19 Ev Group E. Thallner Gmbh Method and device for bonding of chips
TWI791013B (zh) * 2017-03-13 2023-02-01 美商庫利克和索夫工業公司 用於對半導體元件進行超音波接合的方法
CN107946186A (zh) * 2017-11-01 2018-04-20 中国电子科技集团公司第五十五研究所 一种金刚石基GaN‑HEMTs制备方法
CN110078017B (zh) * 2018-01-26 2021-11-05 沈阳硅基科技有限公司 一种贯穿空腔结构硅片的加工方法
CN110164978B (zh) * 2018-02-14 2022-06-21 联华电子股份有限公司 半导体装置以及其制作方法
CN109390303B (zh) * 2018-09-28 2022-01-04 长江存储科技有限责任公司 三维存储器结构的制造方法
CN109449137A (zh) * 2018-11-15 2019-03-08 德淮半导体有限公司 半导体装置及其制造方法
CN110299348A (zh) * 2019-07-02 2019-10-01 贵州大学 一种大功率同步整流器结构的三维集成方法
CN111276469A (zh) * 2020-02-25 2020-06-12 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法

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KR20050025591A (ko) * 2002-07-29 2005-03-14 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ 웨이퍼의 제조방법
KR100618837B1 (ko) * 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
KR100621960B1 (ko) * 2005-05-19 2006-09-08 인터내셔널 비지네스 머신즈 코포레이션 3차원 디바이스 제조 방법
WO2010019889A1 (en) * 2008-08-15 2010-02-18 Qualcomm Incorporated Corrosion control of stacked integrated circuits

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US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
CN100517623C (zh) * 2006-12-05 2009-07-22 中芯国际集成电路制造(上海)有限公司 晶片压焊键合方法及其结构
KR101548173B1 (ko) * 2008-09-18 2015-08-31 삼성전자주식회사 실리콘 다이렉트 본딩(ｓｄｂ)을 이용한 임시 웨이퍼 임시 본딩 방법, 및 그 본딩 방법을 이용한 반도체 소자 및 반도체 소자 제조 방법

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
KR20050025591A (ko) * 2002-07-29 2005-03-14 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ 웨이퍼의 제조방법
KR100618837B1 (ko) * 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
KR100621960B1 (ko) * 2005-05-19 2006-09-08 인터내셔널 비지네스 머신즈 코포레이션 3차원 디바이스 제조 방법
WO2010019889A1 (en) * 2008-08-15 2010-02-18 Qualcomm Incorporated Corrosion control of stacked integrated circuits

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TW201205688A (en) 2012-02-01
SG177817A1 (en) 2012-02-28
KR20120010120A (ko) 2012-02-02
CN105489512A (zh) 2016-04-13
TWI445101B (zh) 2014-07-11
CN105489512B (zh) 2018-01-30
CN102339769A (zh) 2012-02-01

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