TW201205688A - Temporary semiconductor structure bonding methods and related bonded semiconductor structures - Google Patents

Temporary semiconductor structure bonding methods and related bonded semiconductor structures Download PDF

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Publication number
TW201205688A
TW201205688A TW100121500A TW100121500A TW201205688A TW 201205688 A TW201205688 A TW 201205688A TW 100121500 A TW100121500 A TW 100121500A TW 100121500 A TW100121500 A TW 100121500A TW 201205688 A TW201205688 A TW 201205688A
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Taiwan
Prior art keywords
semiconductor structure
wafer
semiconductor
bonded
carrier wafer
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TW100121500A
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Chinese (zh)
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TWI445101B (en
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Mariam Sadaka
Ionut Radu
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Soitec Silicon On Insulator
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Priority claimed from US12/839,203 external-priority patent/US8461017B2/en
Priority claimed from FR1056122A external-priority patent/FR2963162B1/en
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Publication of TW201205688A publication Critical patent/TW201205688A/en
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Publication of TWI445101B publication Critical patent/TWI445101B/en

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Abstract

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Description

201205688 六、發明說明： 【發明所屬之技術領域】 本發明大體而έ係關於可用於形成三維半導體結構之暫 時性半導體晶粒及/或晶圓接合方法，係關於使用暫時性 半導體晶粒及/或晶圓接合方法形成的中間結構，且係關 於用於在暫時性半導體晶圓接合方法中使用的包括一離子 植入區之半導體晶粒及/或晶圓。 【先前技術】 兩個或兩個以上半導體結構之三維（3D)整合可產生微電 子應用之諸多益處。舉例而言，微電子組件之31)整合可導 致改良之電效能及功率消耗，同時減少器件佔據面積之面 積。舉例而言，參見R Garr〇u等人之「The Handb〇〇k 〇f 3D Integration」（Wiley-VCH(20〇8))。 半導體結構之3D整合可藉由以下操作而進行：將一半導 體晶粒附著至一或多個額外半導體晶粒（亦即，晶粒至晶 粒（D2D))，將一半導體晶粒附著至一或多個半導體晶圓 (亦即，晶粒至晶圓（D2W))，以及將一半導體晶圓附著至 一或多個額外半導體晶圓（亦即，晶圓至晶圓（W2w))，或 其組合。 已開發若干製程序列以促進形成3D整合式半導體結構， 包括（例如）個別半導體結構之間的電連接、該等半導體結 構中之一或多者的薄化及個別半導體結構之對準及接合， 等等。詳言之，包含3D整合式半導體結構的該一或多個半 導體結構之薄化可因若干原因而使用，該等原因包括（例 I56586.doc 201205688 :)改良之熱耗散及電阻之減小、然而，可藉由包含 導體結構的該—或多個半導體結構之薄化而產生的 =亦可引人製程複雜化，例如，半導體結構可 處理射^ 因此在使用現有設備及材料之 期間可靶易受到開裂、破裂或其他損害。 對=問題之-提議之解決方案為：將半導體結構（例 ^導體晶圓）結合至加強基板（諸如，另一晶圓（例如， 機竹= 半導體晶圓之處理（例如’薄化）期間提供 ^曰^將半導體晶圓接合至加強基板之製程常常被稱 自丰合」。在處理半導體晶圓之後’可將加強基板 自+導體釋放。 :例而5 ’可使用_點著材料將.—半導體晶圓暫時性地 接。至力口強基板。該黏著材料在半導體晶圓之處理期間 承载與將半導體晶圓與加強基板固持在一起相關聯之力。 ，外’黏著材料及加強基板可充當機械支標件以在半導體 晶圓之處理期間對半導體晶圓提供結構穩定性。許多旋塗 之非晶形聚合物（諸如，聚酿亞胺、苯并環丁稀（bcb)、 NAFION®及光阻材料）已用作用於晶圓接合之黏著材料。 然而，黏著材料在增加之溫度下可為不穩冑#，此情形 可限制可進订半導體器件製造所在的溫度。此外，溶劑或 冷劑蒸汽可在高溫下自此等黏著材料釋放。此製程常常被 稱作「除氣」。除氣可導致在黏著材料中形成氣泡或空 隙。此等氣泡或空隙可導致半導體晶圓與加強基板之間的 非均勻接合強度，且可損害接合之完整性。在丨導體晶圓 156586.doc 201205688 處理之後使用化學移除製程（例如，溶解於溶劑中）完全移 除黏著材料。化學移除製程可為耗時的且對形成於半導體 晶圓上之半導體器件及積體電路器件有損害。因此，當用 於將一半導體晶圓暫時性接合至一加強基板時，黏著接合 可為有問題的。 在處理期間對一半導體晶圓提供支撐之另一方法涉及使 用所4之「直接」晶圓接合製程直接接合兩個半導體基 板。直接晶圓接合製程習知地用於形成為製造用於三維 (3D)器件整合之進階1c所關注的絕緣體上半導體（SeOIp# 構（例如，絕緣體上矽（S0I)結構）β在習知直接晶圓接合製 程中，可在該等晶圓中之至少一者之上形成一表面氧化物 層接著可將该表面氧化物層接合至另一晶圓之表面上的 矽材料或另一氧化物材料。舉例而言，可使半導體晶圓 上之氧化物材料的表面與加強基板之表面接觸且可經由原 子及/或分子黏附而將該兩個結構接合在一起。為了達成 兩個半導體晶圓之間的接合，該等半導體晶圓應具有低表 面粗糙度相容表面化學（亦即，親水性及疏水性），且應至 少實質上無灰塵及其他碎片。 【發明内容】 在些實施例中’本發明包括製造半導體結構之方法。 在第—基板上形成包括一積體電路之至少一部分的一第 。半導體結構。將離子植入至一載體晶圓巾以在該載體晶 圓内形成-弱化區域。將該載體晶圓直接接合至該第一半 導體結構之—第-側。在將該載體晶圓附著至該第-半導 I56586.doc 201205688 體的同時處理該第一半導體結構，且該載體晶圓用以處置 該第一半導體結構。將包括一積體電路之至少一部分的一 第二半導體結構直接接合至該第一半導體結構之一第二 側’該第一半導體結構之該第二側與該載體晶圓直接接合 至的該半導體結構之該第一側對置。將一來自該載體晶圓 之材料層沿該載體晶圓中之該弱化區域與該載體晶圓之一 剩餘部分分離。 本發明亦包括製造半導體結構之方法的額外實施例。將 離子植入至一第一半導體結構中以在其中形成一弱化區 域’且將該第一半導體結構之一表面直接接合至一第二半 導體結構之一表面以形成一包括該第一半導體結構及該第 二半導體結構的經接合之半導體結構。在移除該第二半導 體結構之一部分且曝露至少部分地延伸穿過該第二半導體 結構之至少一導電結構的同時，使用該第一半導體結構處 置6亥經接合之半導體結構。使穿過該第二半導體結構曝露 的該至少一導電結構與一第三半導體結構之至少一導電結 構對準。加熱該經接合之半導體結構及該第三半導體結 構，且回應於加熱該經接合之半導體結構及該第三半導體 、··。構而將穿過該第二半導體結構曝露的該至少一導電結構 直接接合至該第三半導體結構之該至少一導電結構。亦可 回應於加熱該經接合之半導體結構及該第三半導體結構而 /…亥弱化區域ι劃分該第__半導體結構，並使該第一半導體 結構之一部分留在該第二半導體結構上。 本發明之額外實施例包括在如本文中所描述的製造半導 156586.doc 201205688 體結構之方法期間形成的經接合之半導體結構。舉例而 言’-經接合之半導體結構可包括複數個經接合之經處理 之半導體結構，及一載體晶粒或晶圓’該载體晶粒或晶圓 接合至該複數個經接合之經處理之半導體結構中的至少— 經處理之半導體結構。該載體晶粒或晶圓可具有一弱化 區，該弱化區中包含複數個植人之離子，該複數個植入之 離子在距接合㈣複數個經接合之經處理之半導體結構中 的該至少-經處理之半導體結構的該載體晶粒或晶圓之一 表面l〇nm與l〇〇〇nm之間的一平均深度處。 【實施方式】 雖然本說明書以特別地指出並清楚地主張被視為本發明 之㈣例的申請專利範圍結束，但在結合附圖閱讀時，可 更容易地自本發明之實施例之特定實例的指述確定本發明 之實施例的優點。 以下描述提供教細節（諸如，材料_及處理條件）， 以便提供本發明之實施例及其實施方案的詳盡描述。然 而’一般熟習此項技術者將理冑，本發明<實施例可在不 使用此等特定細節之情況下並結合習知製造技術加以實 踐。另外，本文中所提供之描述並不形成用於製造半導體 益件或系統之完整程序流程圖。本文中僅詳細描述用以理 解本發明之實施例所必要的彼等程序動作及結構。本文中 所描述之材料可藉由包括（但不限於）以下各者之任何合適 技術而形成（例如，沈積或生長）：旋塗、毯覆式塗佈、 Bridgeman& Czochraiski 製程、化學氣相沈積（「c」）、 I56586.doc 201205688 電聚增強化學氣相沈積（「PECVD」）、原子層沈積 (「ALD」）、電漿增強ALD或物理氣相沈積（「pVD」）。 雖然本文中所描述及說明的材料可形成為層，但該等材料 不限於層且可以其他三維組態形成。 如本文中所使用，術語「水平」及「垂直」定義元件或 結構相對於晶圓或基板之主平面或表面的相對位置而無關 於晶圓或基板之定向，且為關於所描述之結構之定向而解 譯的正交維度，如描述結構時所參看的圖式中所說明。如 本文中所使用，術語「垂直」意謂並包括實質上垂直於如 所說明之基板或晶圓之主表面的維度，且術語「水平」意 "胃貫質上平行於如所說明之基板或晶圓之主表面並在圖式 之左側與右側之間延伸的維度。如本文中所使用，諸如 「在…上」、「在…之上」、「在...上方」及「在…下方」之 介詞為關於所描述之結構的對應於垂直方向的相對術語。 如本文中所使用，術語「半導體結構」意謂並包括用於 形成半導體器件的任何結構。半導體結構包括（例如）晶粒 及晶圓（例如，載體基板及器件基板），以及包括彼此以三 維方式整合之兩個或兩個以上晶粒及/或晶圓的總成或複 S、’、。構。半導體結構亦包括完全製造之半導體器件，以及 在半導體器件之製造期間形成的中間結構。半導體結構可 包含導電材料、半導電材料及/或不導電材料。 如本文中所使用，術語「經處理之半導體結構」意謂並 包括包括一或多個至少部分地形成之器件結構的任何半導 體結構。經處理之半導體結構為半導體結構之子集，且所 156586.doc 201205688 H處理之半導體結構為半導體結構。 勺：：文中所使用，術語「經接合之半導體結構」意謂並 ::括附著在—起之兩個或兩個以上半導體結構的任何 4 °經接合之半導體結構為半導體結構之子集，且所有 、，接合之半導體結構為半導體結構n包括—或多個 經處理之半導體結構的經接合之半導體結構亦為經處理之 半導體結構。 如本文中所使用’術語「器件結構」意謂並包括經處理 之半導體結構之任何部分’其為，包括或定義待形成於半 導體結構上或半導體結構中的半導體器件之主動組件或被 動組件之至少-部分。舉例而言，器件結構包括積體電路 之主動組件及被動組件，諸如電晶體、轉換器、電容器、 電阻器、導電線、導電介層孔及導電接觸襯墊。° 如本文中所使用，術言吾「穿晶圓互連件」或「TWI」意 謂並包括延伸穿過[半導體結構之至少—部分的任何導 電介層孔，其用以跨越第一半導體結構與第二半導體結構 之間的介面提供第-半導體結構與第二半導體結構之間的 結構互連及/或電互連。穿晶圓互連件在此項技術中亦藉 由諸如「穿石夕介層孔」或「穿基板介層孔」（Tsv)及「穿 晶圓介層孔」或「tWV」之其他術語來指代。彻通常在 -大體上垂直於半導體結構之大體上平坦之主表面的方向 上(亦即，在平行於「Z」轴之方向上)延伸穿過一半導體 結構。 如本文中所使用，當關於一 經處理之半導體結構使用 156586.doc 201205688 時，術語「作用表面」意謂並包括經處理之半導體結構之 曝露的主表面’其已被處理或將被處理以在經處理之半導 體結構之曝露的主表面中及/或曝露的主表面上形成一或 多個器件結構。 如本文中所使用，當關於一經處理之半導體結構使用 時，術語「背表面」意謂並包括在與半導體結構之作用表 面相對的經處理之半導體結構之一側上的經處理之半導體 結構之曝露的主表面。 如本文中所使用，術語「m_v型半導體材料」意謂並包 括主要由以下各者組成之任何材料：來自週期表之iiia族 的一或多種元素（B、A卜Ga、In及Ti)，及來自週期表之 VA族的一或多種元素（n、p、As、Sb及Bi)。 參看圖1，展示一經處理之半導體結構1〇〇，其包括一可 延伸至基板106中並在基板106之表面上及/或之上延伸的 器件區域102。經處理之半導體結構1〇〇包括—作用表面 104及一對置背表面1〇8。作用表面1〇4包含經處理之半導 體結構100的器件區域1〇2之曝露的主表面，而背表面1〇8 包含基板106之曝露之主表面。基板1〇6可包含（例如）一半 導體材料，諸如矽（Si)、鍺（Ge)、III-V半導體材料等。此 外，基板106可包含半導體材料之單晶體，或基礎基板上 的半導體材料之一或多個磊晶層。在額外實施例中，基板 106可包含一或多種介電材料，諸如氧化物（例如，二氧化 石夕（Si〇2)或氧化i呂（八丨2〇3))、氮化物（例如，氮化矽 (Si3N4)、氮化硼（BN)或氮化鋁（A1N))等。 156586.doc -10- 201205688 如將進一步詳細描述，基板106可經選擇以具有用於在 直接晶圓接合製程中使用的所要性質。舉例而言，基板 106可包括具有低彎曲、翹曲及總厚度變化（ττν)之矽晶 圓。如本文中所使用，術語「彎曲」意謂並包括獨立於任 何厚度變化在中線處的半導體基板之中間表面之凹度、曲 率或變形的量測。如本文中所使用，術語「翹曲」意謂並 包括中間表面相對於半導體基板之背側參考平面的最大偏 差與最小偏差之間的差。如本文中所使用，術語「總厚度 變化」及「TTV」各自意謂並包括半導體基板之厚度的最 大.吏化且大體上被定義為在半導體基板上所量測之最小厚 度與最大厚度之間的差《舉例而言，半導體基板之總厚度 變化可藉由在半導體基板上之交叉圖案中的五（5)個或五個 以上位置中量測半導體基板且計算最大量測厚度差來判 定。 具有高翹曲、彎曲及總厚度變化之半導體基板可因若干 原因而不適於用於在直接晶圓接合製程中使用。舉例而 言，在直接晶圓接合製程期間，高翹曲、彎曲及總厚度變 化程度可導致經接合之半導體基板之間的不均勻接觸。此 不均勻接觸可導致直接晶圓接合製程期間的分子黏附之熱 變化及破壞。此外，高翹曲及彎曲值可增加在器件製造期 間半導體基板開裂的風險（歸因於因晶圓黏附至真空夾盤 而誘發的應力sub ’具有低_曲、f曲及總厚度變化 之矽晶圓可用作基板106以為晶圓接合製程提供足夠均勻 性及平坦性。作為非限制性實例，基板1〇6可為一具有以 156586.doc 201205688 下各者之高品質矽晶圓：小於約三十微米（30 μιη)之翹 曲、小於約十微米（10 μίη)之彎曲及小於約一微米（1 μιη)之 總厚度變化。 器件區域102可包括（例如）一或多個器件結構110，器件 結構110可包括嵌入於介電材料114中之導電及/或半導電 元件。器件結構110可包括金屬氧化物半導體（MOS)電晶 體、雙極電晶體、場效電晶體（FET)、二極體、電阻器、 閘流體、整流器及其類似者。器件結構11 〇亦可包含可由 (例如）一或多種金屬（諸如，銅（Cu)、鋁（Α1)或鎢（W))形成 的導電線、跡線、介層孔及襯墊。器件結構11〇亦可包含 一或多個穿晶圓互連件（through wafer interconnect)l 16。 穿晶圓互連件116可藉由在介層孔中沈積一導電材料（諸 如’銅（Cu)、鋁（A1)、鎢（W)、多晶矽或金（Au))而形成。 舉例而言，穿晶圓互連件116可自另一器件結構no延伸並 延伸穿過介電材料114之至少一部分。穿晶圓互連件u6亦 可部分地延伸穿過基板1〇6。 在形成器件區域102之後，可視情況在經處理之半導體 結構100的主表面之上形成接合材料118(以虛線展示）^接 合材料118可由在直接接合製程中展現出與另一材料之良 好黏附的材料形成。舉例而言，接合材料1 i 8可包含一介 電材料，諸如，氧化物（例如，二氧化矽（si02))、氮氧化 物（例如，氮氧化矽（SiON))或氮化物（例如，氮化石夕 (Si3N4))。接合材料118可具有（例如）在約一百奈米（1()〇 nm)與約兩微米（2 μιη)之間的厚度。可使用（例如）化學氣相 156586.doc 201205688 沈積（CVD)、物理氣相沈積（pvD)、原子層沈積（ALD)或電 襞增強化學氣相沈積（PECVD)來在器件區域1〇2上之作用 表面104之上沈積接合材料118。接合材料118可（例如）經平 坦化以減少接合材料118之表面構形。可利用（例如）蝕刻、 研磨及化學機械拋光中之一或多者來使接合材料118平坦 化。 如圖2中所展示’可使圖1中所展示的經處理之半導體結 構100反轉並將其接合至另一半導體結構（在參看圖2所描 述之實施例中，該另一半導體結構包含載體晶圓200)。介 電材料114或（若存在的話）接合材料11 8之主表面與載體晶 圓200之主表面密切接觸。 載體晶圓200可包含一具有低彎曲、翹曲及總厚度變化 (如本文中先前針對基板1〇6所描述）的晶圓，以便為晶圓接 口製私提供足夠均勻性及平坦性。作為非限制性實例，載 體晶圓200可為一具有以下各者之高品質矽晶目：小於約 三十微米（30 μιη)之翹曲、小於約十微米（1〇 μιη)之彎曲， 及小於約一微米（1 μιη)之總厚度變化。 在使、.里處理之半導體結構100的接合材料118之表面與載 體曰曰圓200之表面接觸之前，可視情況執行習知表面清潔 製程以移除表面碎片並形成至少—親水性表面。以實例說 月且非限制，可將經處理之半導體結構100的介電材料U4 或(若存在的話)接合材料m之曝露表面及載體晶圓之 曝露表面分別引入至一包括約5:1:1之比率的水_)、氫 氧化銨(νη4〇η)及過氧化氫(η2〇2)之混合物的溶液，以清 156586.doc •13- 201205688 潔經處理之半導體結構100的介電材料丨i 4或（若存在的話） 接合材料118之曝露表面及載體晶圓2〇〇之曝露表面並賦予 該等曝露表面親水性。 亦可視情況在經處理之半導體結構1〇〇的介電材料114或 (若存在的話）接合材料118之表面及載體晶圓2〇〇之表面中 的至少一者上執行此項技術中被稱為「RCA清潔」之習知 清潔序列，以移除可干擾表面之接合的有機污染物、離子 污染物及金屬污染物。可在接合之前將經處理之半導體結 構100的介電材料114或（若存在的話）接合材料118之表面及 載體晶圓200之表面在去離子（DI)水中重複地漂洗，以防 止表面粒子並維持親水性◎可使用諸如熱接合'熱壓接合 或熱超音波接合之技術將經處理之半導體結構1〇〇的介電 材料114或（若存在的話）接合材料i 1 8接合至載體晶圓2 〇 〇， 以形成一經接合之半導體結構3〇〇。 在一些實施例中，可將經處理之半導體結構1〇〇直接接 合至載體晶圓200而在其間不使用任何中間黏著材料 '經 處理之半導體結構⑽與载體晶圓細之間的原子或分子接 合的性質將取決於經處理之半導體結構1⑽及載體晶圓綱 中之每一者的材料組成。因此，根據-些實施例，可在 (例如）氧切及氮切中之至少—者財、氧切及氮化 矽中之至少一者之間提供直接原子或分子接合。 參看圖3 ’在如圖2中所展示將經處理之半導體結構100 接合至載體晶圓200之前，可將載體晶圓綱製造為包括一 其中具有-轉移區域204的半導體材料2〇2，該轉移區域 156586.doc 201205688 係藉由植人區2G6(藉由虛線表示）定義。轉移區域⑽可 藉由將離子物質植入至载體晶圓之半導體材料逝中以 形成植人區206而形成、舉例而言，離子物質可為氣離 子、惰性氣體離子或氟離子β可將離子物質植入至載體晶 圓_中’以沿載體晶圓之一具有離子之岭值濃度的區 域形成植入區206。離子植入可在載體晶圓测内形成一弱 化區’當載體晶圓_經受高溫時或在向載體晶圓施加 機械力（諸如，努切力）後’載體晶圓2〇〇可能易受到沿該弱 化區之斷裂或分裂。可調整離子植入參數以防止在將經 處理之半導體結構⑽接合至載體晶圓2叫圖Μ期間載體晶 沿植人區206分裂或斷裂。此情形使得載體晶圓· 月㈣即將描述之稍後處理階段期間劃分成兩個個別部 分0 作為一非限制性實例，離子物質可包含氫離子、氨離子 及蝴離子中之一或多者。該一或多種離子物質可以約I" 離子數/cm2與2χ 1〇丨7雜早童Ww2 4日日 離子數/cm之間或ιχ1〇ΐ6離子數/cm2與 I’17離子數W之間的劑量植入。該一或多種離子物質 可以約十千電子伏特（1GKeV)與-百五十千f子伏特（150 蝴之間的能量植入。將離子植入至載體晶圓_中以形 成植入區206的深度至少部分係用以將離子植入至載體晶 回2〇0中之能量的函數。因此，可藉由選擇性地控制植入 離子之能量而在載體晶圓扇中之所要深度處形成植入區 鹰。载體晶圓綱内之植人區咖的深度⑴可對應於可隨 後破轉移至經處理之半導體結構⑽的半導體材料2〇2之層 156586.doc 201205688 的所要厚度及/或體積，如下文進一步詳細地描述。作為 一非限制性實例，可藉由經選擇以在約十奈米（1〇 nm)與 約一千奈米（1000 nm)(亦即，約100 A至約10000 A)之間的 深度D1處形成植入區2〇6的能量將原子物質植入至載體晶 圓200中。 可視情況在最接近植入區206的載體晶圓2〇〇之主表面之 上形成另一接合材料218，且亦可在形成植入區2〇6之前在 載體晶圓200之主表面之上形成另一接合材料218。接合材 料218可由展現出與介電材料114或（若存在的話）上覆經處 理之半導體結構100的接合材料118(圖1及圖2)之良好分子 黏附的材料形成。接合材料218可由一或多種介電材料（諸 如’二氧化矽（Si02)、氮氧化矽（Si〇xNy)及氮化矽（Si3N4)) 形成。接合材料21 8可具有在約一百奈米（丨〇〇 nm)與約兩 微米（2 μηι)之間的厚度。以實例說明且非限制，載體晶圓 200可由石夕材料形成且可藉由執行一習知熱氧化製程而在 載體晶圓200上形成包含二氧化矽（Si〇2)之接合材料21 8。 亦可使用（例如）化學氣相沈積（CVD)、物理氣相沈積 (PVD)、原子層沈積（ALD)或電漿增強化學氣相沈積 (PECVD)來沈積接合材料218。 返回參看圖2’可藉由使載體晶圓2〇〇之曝露表面（亦 即’半導體材料202或（若存在的話）接合材料218之曝露表 面）緊靠經處理之半導體結構100(亦即，介電材料114或（若 存在的話）接合材料118)的曝露表面而將載體晶圓2〇〇接合 至經處理之半導體結構丨00，以形成經接合之半導體結構201205688 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a temporary semiconductor die and/or wafer bonding method that can be used to form a three-dimensional semiconductor structure, using a temporary semiconductor die and/or Or an intermediate structure formed by a wafer bonding method, and relates to a semiconductor die and/or wafer including an ion implantation region for use in a temporary semiconductor wafer bonding method. [Prior Art] Three-dimensional (3D) integration of two or more semiconductor structures can yield a number of benefits for microelectronic applications. For example, 31) integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area occupied by the device. For example, see "The Handb〇〇k 〇f 3D Integration" by R Garr〇u et al. (Wiley-VCH (20〇8)). The 3D integration of the semiconductor structure can be performed by attaching a semiconductor die to one or more additional semiconductor dies (ie, die to die (D2D)), attaching a semiconductor die to the Or a plurality of semiconductor wafers (ie, die to wafer (D2W)), and attaching a semiconductor wafer to one or more additional semiconductor wafers (ie, wafer to wafer (W2w)), Or a combination thereof. Several programming sequences have been developed to facilitate the formation of 3D integrated semiconductor structures, including, for example, electrical connections between individual semiconductor structures, thinning of one or more of such semiconductor structures, and alignment and bonding of individual semiconductor structures, and many more. In particular, thinning of the one or more semiconductor structures including 3D integrated semiconductor structures can be used for a number of reasons, including (example I56586.doc 201205688 :) improved heat dissipation and reduced resistance However, the result of the thinning of the semiconductor structure or the plurality of semiconductor structures including the conductor structure can also be complicated, for example, the semiconductor structure can process the radiation, and thus can be used during the use of existing equipment and materials. The target is susceptible to cracking, cracking or other damage. The solution to the problem is to combine a semiconductor structure (eg, a conductor wafer) to a reinforcement substrate (such as another wafer (eg, machine bamboo = semiconductor wafer processing (eg, 'thinning') The process of bonding a semiconductor wafer to a reinforced substrate is often referred to as "richness." After processing the semiconductor wafer, the reinforced substrate can be released from the + conductor. Example: 5' can be used _ point material will The semiconductor wafer is temporarily connected to the strong substrate. The adhesive material carries the force associated with holding the semiconductor wafer and the reinforcing substrate together during the processing of the semiconductor wafer. The external 'adhesive material and reinforcement The substrate can act as a mechanical support to provide structural stability to the semiconductor wafer during processing of the semiconductor wafer. Many spin-on amorphous polymers (eg, polyacrylonitrile, benzocyclobutene (bcb), NAFION) ® and photoresist materials have been used as adhesion materials for wafer bonding. However, adhesive materials can be unstable at increased temperatures, which limits the temperature at which semiconductor devices can be fabricated. In addition, solvent or refrigerant vapors can be released from such adhesive materials at elevated temperatures. This process is often referred to as "degassing." Degassing can result in the formation of bubbles or voids in the adhesive material. Resulting in non-uniform bonding strength between the semiconductor wafer and the reinforcing substrate, and can compromise the integrity of the bonding. Complete removal after processing of the germanium conductor wafer 156586.doc 201205688 using a chemical removal process (eg, dissolved in a solvent) Adhesive material. The chemical removal process can be time consuming and detrimental to semiconductor devices and integrated circuit devices formed on semiconductor wafers. Therefore, when used to temporarily bond a semiconductor wafer to a reinforced substrate, Adhesive bonding can be problematic. Another method of providing support to a semiconductor wafer during processing involves directly bonding two semiconductor substrates using a "direct" wafer bonding process of 4. The direct wafer bonding process is conventionally used. Insulator-on-semiconductor (SeOIp# structure (for example, on-insulator (S0I)) for the formation of advanced 1c for three-dimensional (3D) device integration Structure [beta] In a conventional direct wafer bonding process, a surface oxide layer can be formed over at least one of the wafers and then bonded to the surface of the other wafer. A tantalum material or another oxide material. For example, the surface of the oxide material on the semiconductor wafer can be brought into contact with the surface of the reinforcing substrate and the two structures can be bonded together via atomic and/or molecular adhesion. In order to achieve bonding between two semiconductor wafers, the semiconductor wafers should have low surface roughness compatible surface chemistry (i.e., hydrophilicity and hydrophobicity) and should be at least substantially free of dust and other debris. SUMMARY OF THE INVENTION In some embodiments, the invention includes a method of fabricating a semiconductor structure. A first semiconductor structure including at least a portion of an integrated circuit is formed on a first substrate. The ions are implanted into a carrier wafer to form a weakened region within the carrier crystal. The carrier wafer is bonded directly to the -th side of the first semiconductor structure. The first semiconductor structure is processed while the carrier wafer is attached to the first semiconductor substrate, and the carrier wafer is used to treat the first semiconductor structure. Directly bonding a second semiconductor structure including at least a portion of an integrated circuit to a second side of the first semiconductor structure, the second side of the first semiconductor structure and the semiconductor directly bonded to the carrier wafer The first side of the structure is opposite. A layer of material from the carrier wafer is separated from the remainder of one of the carrier wafers along the weakened region of the carrier wafer. The invention also includes additional embodiments of a method of fabricating a semiconductor structure. Implanting ions into a first semiconductor structure to form a weakened region therein and directly bonding one surface of the first semiconductor structure to a surface of a second semiconductor structure to form a first semiconductor structure and A bonded semiconductor structure of the second semiconductor structure. The semiconductor structure is disposed using the first semiconductor structure while the portion of the second semiconductor structure is removed and exposed to at least partially extend through at least one of the second semiconductor structures. Aligning the at least one electrically conductive structure exposed through the second semiconductor structure with at least one electrically conductive structure of a third semiconductor structure. The bonded semiconductor structure and the third semiconductor structure are heated and in response to heating the bonded semiconductor structure and the third semiconductor. The at least one electrically conductive structure exposed through the second semiconductor structure is directly bonded to the at least one electrically conductive structure of the third semiconductor structure. The __semiconductor structure may also be divided in response to heating the bonded semiconductor structure and the third semiconductor structure, and leaving a portion of the first semiconductor structure on the second semiconductor structure. Additional embodiments of the present invention include bonded semiconductor structures formed during the method of fabricating a semiconductor structure of a semiconductor 156586.doc 201205688 as described herein. For example, a 'bonded semiconductor structure can include a plurality of bonded processed semiconductor structures, and a carrier die or wafer that is bonded to the plurality of bonded processes At least the processed semiconductor structure in the semiconductor structure. The carrier die or wafer may have a weakened region, the weakened region comprising a plurality of implanted ions, the plurality of implanted ions being at least one of the bonded (four) plurality of bonded processed semiconductor structures - an average depth between the surface of one of the carrier grains or wafers of the processed semiconductor structure between 10 nm and 10 nm. [Embodiment] Although the specification specifically states and clearly claims that the scope of the patent application of the invention is considered to be the end of the scope of the invention, the specific examples of the embodiments of the invention can be more easily read from the drawings. The description refers to the advantages of embodiments of the invention. The following description provides the details of the teachings, such as materials and processing conditions, in order to provide a detailed description of the embodiments of the invention and the embodiments thereof. However, it will be apparent to those skilled in the art that the present invention may be practiced without departing from the specific details. In addition, the description provided herein does not form a complete program flow diagram for the manufacture of semiconductor benefits or systems. Only the program actions and structures necessary to understand the embodiments of the present invention are described in detail herein. The materials described herein can be formed (eg, deposited or grown) by any suitable technique including, but not limited to, spin coating, blanket coating, Bridgeman & Czochraiski process, chemical vapor deposition ("c"), I56586.doc 201205688 Electropolymerization Enhanced Chemical Vapor Deposition ("PECVD"), Atomic Layer Deposition ("ALD"), Plasma Enhanced ALD or Physical Vapor Deposition ("pVD"). While the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three dimensional configurations. As used herein, the terms "horizontal" and "vertical" define the relative position of an element or structure relative to the principal plane or surface of the wafer or substrate without regard to the orientation of the wafer or substrate, and with respect to the described structure. The orthogonal dimensions of the orientation and interpretation are as illustrated in the schema referred to in describing the structure. As used herein, the term "vertical" means and includes a dimension that is substantially perpendicular to the major surface of the substrate or wafer as illustrated, and the term "horizontal" is meant to be parallel to the mass as described. The dimension of the main surface of the substrate or wafer and extending between the left and right sides of the drawing. As used herein, the prepositions such as "on", "above", "above" and "below" are relative terms that correspond to the vertical direction of the described structure. As used herein, the term "semiconductor structure" means and includes any structure for forming a semiconductor device. The semiconductor structure includes, for example, a die and a wafer (eg, a carrier substrate and a device substrate), and an assembly or complex S, including two or more dies and/or wafers integrated in three dimensions with each other. ,. Structure. Semiconductor structures also include fully fabricated semiconductor devices, as well as intermediate structures formed during the fabrication of semiconductor devices. The semiconductor structure can comprise a conductive material, a semiconductive material, and/or a non-conductive material. As used herein, the term "treated semiconductor structure" means and includes any semiconductor structure including one or more at least partially formed device structures. The processed semiconductor structure is a subset of the semiconductor structure, and the semiconductor structure processed by 156586.doc 201205688 H is a semiconductor structure. Spoon: As used herein, the term "bonded semiconductor structure" means: and includes any 4° bonded semiconductor structure attached to two or more semiconductor structures as a subset of the semiconductor structure, and All, the bonded semiconductor structure is a semiconductor structure n. The bonded semiconductor structure comprising - or a plurality of processed semiconductor structures is also a processed semiconductor structure. The term 'device structure' as used herein means and includes any portion of a processed semiconductor structure that includes or defines active or passive components of a semiconductor device to be formed on or in a semiconductor structure. At least - part. For example, the device structure includes active and passive components of the integrated circuit, such as transistors, converters, capacitors, resistors, conductive lines, conductive via holes, and conductive contact pads. ° As used herein, the term "through-wafer interconnect" or "TWI" means and includes any conductive via hole extending through at least a portion of the semiconductor structure for crossing the first semiconductor. The interface between the structure and the second semiconductor structure provides structural interconnections and/or electrical interconnections between the first semiconductor structure and the second semiconductor structure. Through-wafer interconnects are also used in the art by other terms such as "through the hole" or "through the via" (Tsv) and "through the via" or "tWV". To refer to. The pattern extends generally through a semiconductor structure in a direction substantially perpendicular to a substantially planar major surface of the semiconductor structure (i.e., in a direction parallel to the "Z" axis). As used herein, when referring to a processed semiconductor structure, 156586.doc 201205688, the term "active surface" means and includes the exposed major surface of the processed semiconductor structure 'which has been processed or will be processed to One or more device structures are formed in the exposed major surface of the treated semiconductor structure and/or on the exposed major surface. As used herein, the term "back surface" as used with respect to a treated semiconductor structure means and includes a processed semiconductor structure on one side of a processed semiconductor structure opposite the active surface of the semiconductor structure. The exposed main surface. As used herein, the term "m_v type semiconductor material" means and includes any material consisting essentially of one or more elements (B, A, Ga, In, and Ti) from group iiia of the periodic table, And one or more elements (n, p, As, Sb, and Bi) from the VA group of the periodic table. Referring to Fig. 1, a processed semiconductor structure 1 is shown that includes a device region 102 that extends into and extends over and/or over the surface of substrate 106. The processed semiconductor structure 1 includes an active surface 104 and a pair of back surfaces 1〇8. The active surface 1〇4 contains the exposed major surface of the device region 1〇2 of the processed semiconductor structure 100, while the back surface 1〇8 includes the exposed major surface of the substrate 106. Substrate 1 6 may comprise, for example, half of a conductor material such as germanium (Si), germanium (Ge), III-V semiconductor material, and the like. In addition, substrate 106 can comprise a single crystal of semiconductor material, or one or more epitaxial layers of semiconductor material on a base substrate. In additional embodiments, substrate 106 may comprise one or more dielectric materials such as an oxide (eg, SiO 2 or oxidized i ( 2 〇 3 ), nitride (eg, Niobium nitride (Si3N4), boron nitride (BN) or aluminum nitride (A1N)). 156586.doc -10- 201205688 As will be described in further detail, substrate 106 can be selected to have the desired properties for use in a direct wafer bonding process. For example, substrate 106 can include twin circles having low bends, warpage, and total thickness variations (ττν). As used herein, the term "bending" means and includes measurements of the concavity, curvature or deformation of the intermediate surface of the semiconductor substrate at any center of the thickness variation. As used herein, the term "warping" means and includes the difference between the maximum deviation and the minimum deviation of the intermediate surface relative to the backside reference plane of the semiconductor substrate. As used herein, the terms "total thickness variation" and "TTV" each mean and include the maximum thickness of a semiconductor substrate and is generally defined as the minimum thickness and maximum thickness measured on a semiconductor substrate. The difference between the semiconductor substrates, for example, the total thickness variation of the semiconductor substrate can be determined by measuring the semiconductor substrate in five (5) or more positions in the cross pattern on the semiconductor substrate and calculating the maximum measured thickness difference. . Semiconductor substrates having high warpage, bending, and total thickness variations may be unsuitable for use in direct wafer bonding processes for a number of reasons. For example, during direct wafer bonding processes, high warpage, bending, and overall thickness variations can result in uneven contact between the bonded semiconductor substrates. This uneven contact can result in thermal changes and damage to molecular adhesion during direct wafer bonding processes. In addition, high warpage and bending values increase the risk of cracking of the semiconductor substrate during device fabrication (due to the stress sub' induced by wafer sticking to the vacuum chuck with low _ curvature, f curvature, and total thickness variation. The wafer can be used as the substrate 106 to provide sufficient uniformity and flatness for the wafer bonding process. As a non-limiting example, the substrate 〇6 can be a high quality 矽 wafer having a size of 156586.doc 201205688: less than A warpage of about thirty micrometers (30 μm), a bend of less than about ten micrometers (10 μίη), and a total thickness variation of less than about one micrometer (1 μm). Device region 102 can include, for example, one or more device structures. 110. The device structure 110 can include conductive and/or semi-conductive elements embedded in a dielectric material 114. The device structure 110 can include a metal oxide semiconductor (MOS) transistor, a bipolar transistor, a field effect transistor (FET). , a diode, a resistor, a thyristor, a rectifier, and the like. The device structure 11 〇 can also include, for example, one or more metals such as copper (Cu), aluminum (Α1), or tungsten (W). Formed conductive The device structure 11 can also include one or more through wafer interconnects 16. The through wafer interconnects 116 can be through the vias. Forming a conductive material such as 'copper (Cu), aluminum (A1), tungsten (W), polysilicon or gold (Au)). For example, the through-wafer interconnect 116 may be from another device structure No extends and extends through at least a portion of the dielectric material 114. The through-wafer interconnect u6 may also extend partially through the substrate 1 〇 6. After forming the device region 102, optionally in the processed semiconductor structure 100 A bonding material 118 is formed over the major surface (shown in phantom). The bonding material 118 may be formed of a material that exhibits good adhesion to another material in a direct bonding process. For example, the bonding material 1 i 8 may comprise a dielectric A material such as an oxide (for example, cerium oxide (si02)), an oxynitride (for example, cerium oxynitride (SiON)), or a nitride (for example, cerium nitride (Si3N4)). The bonding material 118 may have ( For example) at about 100 nanometers (1 () 〇 nm) and about two microns (2 The thickness between μιη) can be used, for example, by chemical vapor 156586.doc 201205688 deposition (CVD), physical vapor deposition (pvD), atomic layer deposition (ALD) or electro-time enhanced chemical vapor deposition (PECVD). Bonding material 118 is deposited over active surface 104 on device region 1-2. Bonding material 118 may, for example, be planarized to reduce the surface configuration of bonding material 118. For example, etching, grinding, and chemical mechanical polishing may be utilized. One or more of them are used to planarize the bonding material 118. As shown in FIG. 2, the processed semiconductor structure 100 shown in FIG. 1 can be inverted and bonded to another semiconductor structure (in the embodiment described with reference to FIG. 2, the other semiconductor structure includes Carrier wafer 200). The major surface of dielectric material 114 or, if present, bonding material 118 is in intimate contact with the major surface of carrier wafer 200. The carrier wafer 200 can include a wafer having low bend, warp, and total thickness variations (as previously described herein for the substrate 1 〇 6) to provide sufficient uniformity and flatness for wafer interface fabrication. As a non-limiting example, the carrier wafer 200 can be a high quality crystallite having a warp of less than about thirty micrometers (30 μm), a bend of less than about ten micrometers (1 μm), and A total thickness change of less than about one micron (1 μm). Prior to contacting the surface of the bonding material 118 of the semiconductor structure 100 processed in the process with the surface of the carrier dome 200, a conventional surface cleaning process can be performed to remove surface debris and form at least a hydrophilic surface. By way of example and without limitation, the dielectric material U4 of the processed semiconductor structure 100 or, if present, the exposed surface of the bonding material m and the exposed surface of the carrier wafer may each be introduced to include a ratio of about 5:1: a solution of a mixture of water_), ammonium hydroxide (νη4〇η) and hydrogen peroxide (η2〇2) in a ratio of 1 to 156586.doc • 13-201205688 cleaned semiconductor structure 100 dielectric material丨i 4 or, if present, the exposed surface of bonding material 118 and the exposed surface of carrier wafer 2 and imparts hydrophilicity to the exposed surfaces. It is also possible to perform the technique in the art by performing at least one of the surface of the processed semiconductor structure 114 or the surface of the bonding material 118 and the surface of the carrier wafer 2〇〇. A conventional cleaning sequence for "RCA Cleaning" to remove organic, ionic, and metallic contaminants that can interfere with the bonding of surfaces. The surface of the dielectric material 114 of the processed semiconductor structure 100 or, if present, the surface of the bonding material 118 and the surface of the carrier wafer 200 may be repeatedly rinsed in deionized (DI) water prior to bonding to prevent surface particles and Maintaining Hydrophilicity ◎ The dielectric material 114 of the processed semiconductor structure or, if present, the bonding material i 1 8 can be bonded to the carrier wafer using techniques such as thermal bonding 'thermocompression bonding or thermal ultrasonic bonding. 2 〇〇 to form a bonded semiconductor structure 3〇〇. In some embodiments, the processed semiconductor structure 1 can be directly bonded to the carrier wafer 200 without any intermediate bonding material between the processed semiconductor structure (10) and the carrier wafer fine or The nature of the molecular bonding will depend on the material composition of each of the processed semiconductor structure 1 (10) and the carrier wafer. Thus, in accordance with some embodiments, direct atomic or molecular bonding can be provided between at least one of, for example, oxygen cutting and nitrogen cutting. Referring to FIG. 3, prior to bonding the processed semiconductor structure 100 to the carrier wafer 200 as shown in FIG. 2, the carrier wafer can be fabricated to include a semiconductor material 2〇2 having a-transfer region 204 therein. The transfer area 156586.doc 201205688 is defined by the implanted area 2G6 (represented by the dashed line). The transfer region (10) may be formed by implanting an ionic species into the semiconductor material of the carrier wafer to form the implanted region 206. For example, the ionic species may be a gas ion, an inert gas ion, or a fluoride ion β. The ionic species are implanted into the carrier wafer to form an implanted region 206 in a region having a concentration of ions at one of the carrier wafers. Ion implantation can form a weakened zone in the carrier wafer. 'When the carrier wafer is subjected to high temperatures or after applying a mechanical force (such as a Nunch force) to the carrier wafer, the carrier wafer 2 may be susceptible to Breaking or splitting along the weakened zone. The ion implantation parameters can be adjusted to prevent the carrier crystal from splitting or breaking along the implanted region 206 during bonding of the processed semiconductor structure (10) to the carrier wafer 2. This situation causes the carrier wafer to be divided into two individual portions during a later processing stage to be described as a non-limiting example. The ionic species may comprise one or more of hydrogen ions, ammonia ions, and butterfly ions. The one or more ionic substances may be between about 1" ion number/cm2 and 2χ1〇丨7 miscellaneous children Ww2 4 day ion number/cm or ιχ1〇ΐ6 ion number/cm2 and I'17 ion number W The dose is implanted. The one or more ionic species may be implanted between about ten kiloelectron volts (1GKeV) and one hundred and fifty thousand volts (150 ounces of energy. Implant ions into the carrier wafer to form the implanted region 206 The depth is at least partially a function of the energy used to implant ions into the carrier crystal back to 〇 0. Thus, it can be formed at a desired depth in the carrier wafer fan by selectively controlling the energy of the implanted ions. Implantation zone eagle. The depth (1) of the implanted area within the carrier wafer can correspond to the desired thickness of the layer 156586.doc 201205688 of the semiconductor material 2〇2 that can subsequently be transferred to the processed semiconductor structure (10) and/or Or volume, as described in further detail below. As a non-limiting example, it can be selected to be at about ten nanometers (1 〇 nm) and about one thousand nanometers (1000 nm) (ie, about 100 A). The energy forming the implant region 2〇6 at a depth D1 between about 10000 A) implants the atomic material into the carrier wafer 200. The carrier wafer 2 closest to the implant region 206 can be used as the case may be. Another bonding material 218 is formed over the surface, and may also be formed in the implanted region 2〇6 Another bonding material 218 is formed over the major surface of the carrier wafer 200. The bonding material 218 can be formed by bonding material 118 that exhibits overlying the dielectric material 114 or, if present, the processed semiconductor structure 100 (Fig. 1 The material of good molecular adhesion of Figure 2) is formed. The bonding material 218 may be formed of one or more dielectric materials such as 'cerium oxide (SiO 2 ), yttrium oxynitride (Si〇 x Ny), and tantalum nitride (Si 3 N 4 )). The material 21 8 may have a thickness between about one hundred nanometers (丨〇〇 nm) and about two micrometers (2 μm). By way of example and not limitation, the carrier wafer 200 may be formed of a stone material and may be A conventional thermal oxidation process is performed to form a bonding material 218 comprising cerium oxide (Si〇2) on the carrier wafer 200. For example, chemical vapor deposition (CVD), physical vapor deposition (PVD) can also be used. , Atomic Layer Deposition (ALD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) to deposit bonding material 218. Referring back to Figure 2, the exposed surface of the carrier wafer 2 can be removed (i.e., 'semiconductor material 202 Or (if present) the exposure of the bonding material 218 The carrier wafer 2 is bonded to the processed semiconductor structure 丨00 in close proximity to the exposed surface of the processed semiconductor structure 100 (ie, the dielectric material 114 or, if present, the bonding material 118), Forming a bonded semiconductor structure

156586.doc _16_ S 201205688 3〇〇。可在室溫下或在高溫(例如 (100eC ))及高壓下將进胁曰门 乂间於攝氏一百度 4下將载體晶圓200接合至經 構100歷時足夠時間量， 導體結 乂將接合材料u 8鱼本邕 202或(若存在的話)接合 “導體材料 明，可藉由將瘦卢…以非限制性實例說 力J猎由將經處理之半導體 至在約攝氏一百度⑽。〇與約攝氏0及載體晶圓200曝露 ”解砗心、 則攝氏四百度(4〇(TC )之間的 夺〇/刀鐘與120分鐘之間的時間以接合載體日圓 200與經處理之半導體 載體日曰圓 眘竑如由-r . 叩執仃—退火製程。在一些 在不使用黏著材料的情況下將經處理之半導 體結構100接合至載體晶圓2〇〇， 外可能由此點著劑之使用產生的進月=減乂或消除對另 壓力限制。 肖產生的進-步處理動作的溫度及 參看圖4 ’在接合載體晶圓2〇〇與經處理之半導體 100以形成經接合之半導體結構3〇〇之後，可將基板二之 -部分自經處理之半導體結構⑽的主表面（例如，背表面 108)移除以曝露穿過基板⑽的穿晶圓互連件116之表面。 舉例而言，可使用研磨製程、習知化學機械拋光製程、各 向異性蝕刻製程或其組合來移除基板106之該部分。在一 二實施例中’基板106可視情況包括一諸如氧化物材料之 触刻終止材料120(其以虛線展示）。姓刻終止材料120可垂 直地定位於基板106内之各種位置處。舉例而言，敍刻終 止材料120可定位於基板1〇6内、在穿晶圓互連件〗16之表 面117之上方、下方或與表面U7水平之位置。 作為一非限制性實例，可藉由（例如）將載體晶圓2〇〇固 156586.doc -17· 201205688 疋在真二火盤上且相抵於一旋轉之拋光襯塾按壓基板l〇6 之曝露表面而執行一研磨及化學機械拋光製程，以相對於 穿晶圓互連件U6及蝕刻終止材料120(若存在的話）移除基 板106之部分，同時化學上及/或物理上活性（亦即，研磨 劑）漿料移除基板1 〇6之材料。 作為另一非限制性實例，可藉由將一包括氫氧化鉀 (KOH)或四曱基銨氫氧化物（TMAH)之溶液引入至基板ι〇6 之曝露表面而執行濕式蝕刻製程，以相對於穿晶圓互連件 116及蝕刻終止材料（若存在的話）移除基板106之部分。載 體晶圓200用以處置經處理之半導體結構1〇〇，並在使基板 106薄化以曝露穿晶圓互連件工16之表面期間為經處理之半 導體結構100提供機械支撐。基板106之剩餘部分可具有約 二分之一微米（〇·5 μΓη)至約一百微米（1〇〇 μπι)之厚度d2。 如圖3中所展示，可使經接合之半導體結構3〇〇反轉與 另一經處理之平坦半導體結構400對準並與另一經處理之 平坦半導體結構400接觸，如藉由定向箭頭表示，舉例而 言，經接合之半導體結構300的穿晶圓互連件116之曝露表 面可與經處理之半導體結構400之作用表面4〇4上的曝露之 導電襯墊420接觸並接合至曝露之導電襯墊42〇。 經處理之半導體結構4〇〇(類似經處理之半導體結構1〇〇) "Τ包括 包括盗件結構4 1 0之件區域4 〇 2。器件區域4 〇 2 可延伸至基板406中並在基板406之表面上及/或表面之上 延伸。基板406可包含如先前關於基板106所描述之基板。 類似地，器件區域402之器件結構410可包括如先前關於圖 I56586.doc •18· 201205688 1之器件結構11 〇所描述之器件結構。在一些實施例中，經 處理之半導體結構400的器件區域4〇2可具有至少實質上與 經處理之半導體結構100的器件區域丨〇2相同之組態。 在形成經處理之半導體結構4〇〇的器件區域4〇2之後，可 在斋件區域402之上形成一或多個導電結構（諸如，導電襯 墊420)。導電襯墊42〇可包括一或多種導電材料，諸如一 或多種金屬（例如，銅（CU)、鋁（Ai)、鎢（|)、多晶矽及/或 金（Au)^舉例而言，可在後段製程（BE〇L)製程中在經處 理之半導體結構400上形成導電襯墊420。在一些實施例 中，可藉由在介電材料414之上沈積一導電材料（未圖示）且 使用光微影技術來圖案化該導電材料以形成導電襯墊42〇 而形成導電襯塾420。在其他實施例中，可藉自以下操作 而形成導電襯墊420 :將導電材料沈積於介電材料414中之 複數個開口（未圖示）_，且執行化學機械拋光縱）製程 二移除上覆該等開σ的導電材料之部分（通常稱作「镶嵌 製程」）。可藉由使經處理之半導體結構1〇〇之穿晶圓互連 件116與經處理之半導體結構4〇〇之導電襯塾420對準並接 口而使經接合之半導體結構則與經處理之半導體結構彻 在結構上及電力上彼此耦接。 參看圖6,經處理之半導體結構1〇〇可接合至經處理之半 導體結構400以形成另—經接合之半導體結構_，其中經 處理之半導體結構i 〇 〇之穿晶圓互連件i i 6在結構上及電力 亡耗接至經處理之半導體結構彻之導電襯塾420。在一些 實^例中可使用直接金屬至金屬接合製程(諸如，熱壓 156586.doc 19 201205688 接合製程、非熱壓接合或共晶接合製程）將穿晶圓互連件 116直接接合至導電襯墊·。舉例而言，穿晶圓互連件 116及導電襯墊侧可各自由鋼形成，且可藉由以下操作來 執行低溫銅至鋼接合製程··將經接合之半導體結構则及 經處理之半導體結構40叫露至在約攝氏—百度（⑽〇與 約攝氏四百度（4〇〇。〇)之間的溫度歷時足夠時間量，以用於 將穿晶圓互連件116及導電襯墊接合至彼此。 在其他實施例中’可使用直接晶圓接合製程將各別經處 理之半導體結構！⑽及之作用表面⑽及4〇4(圖5)彼此接 合，其中作用表面108及404可包含導電（例如，金屬）區域 及非導電(例如，介電質)區域且直接晶圓接合製程同時接 合金屬至金屬與介電質至介電質。 可在作用表面108及404中之一或多者之上形成一可選接 合材料。如藉由圖5之非限制性實例說明，可視情況使用 氧化物沈積製程（諸如，低溫電漿沈積製程）在基板1〇6之上 形成一（例如）包含二氧化矽（Si〇2)材料122(以虛線展示）之 可選介電質接合材料。可選接合材料122可進一步經平坦 化以曝露導電襯塾42〇 ;此平坦化可（例藉由化學機械抛 光製程來執行。 可使用氧化物至氧化物接合製程（諸如，參看圖4所描述 之氧化物至氧化物接合製程）將二氧化矽材料122接合至經 處理之半導體結構400之介電材料414。舉例而言，可在室 溫下或在高溫（例如，至少高於攝氏一百度（1〇〇它））下將二 氧化矽材料m接合至介電材料414。金屬至金屬接合製程 156586.doc •20· 201205688 及氧化物至氧化物接合製程可在低溫（亦即，小於約攝氏 四百度（4GGt)之溫度）下執行，且因此，避免損害經處理 之半導體結構100及400的器件區域1〇2及4〇2。在根據本發 明之方法執行後段製程（BE〇L)製程之後垂直地堆疊經處理 之半導體結構HK)及_使得能夠在接合製程期間在經處理 之半導體結構100與經處理之半導體結構4〇〇之間形成導電 互連（例如，穿晶圓互連件116與導電襯墊420之耦接）。 在半導體結構100與半導體結構400接合期間或接合完成 後，可將載體晶圓200之材料之一部分2〇2，(圖5)盥經接人 之半導體結構500分離（亦即，拆離），留下轉移;材料^ 2〇2"仍在經處理之半導體結構1〇〇上。载體晶圓2〇〇之材料 之部分202,的分離可藉由各種化學、熱或機械製程(諸如， 藉由研磨製程、蝕刻製程、拋光製程或起離製程)來執 订。舉例而s，可執行—單—退火製程，以將半導體結構 100與40G兩者接合至彼此，同時將載體晶圓之材料之部分 2〇2’與轉移之材料層2〇2”分離㈣，拆離)。可藉由以下 知作來執打退火製程：使經處理之半導體結構⑽之主表 面（亦即基板1〇6之曝露主表面及介層孔插塞11〇之曝露 表面）與經處理之半導體結構400之主表面（亦即，介電材料 414之曝露主表面及導電襯墊420之曝露表面）接觸，且在 約攝氏二百度（2GG°C )與約攝氏四百度（4GGt )之間的溫度 下退火。退火製程可同時將半導體結構100與半導體結構 4〇0兩者接合（亦即，將穿晶圓互連件116接合至導電襯塾 420)，並使載體晶圓2〇〇之材料之部分與轉移之半導體 156586.doc -21· 201205688 層202"分裂。 以貫例說明且非限制’行業中稱為SMART-CUT™製程 之製程可用以將材料之部分202’與轉移之材料層2〇2 "分離 或拆離。此等製程詳細描述於以下各專利中：（例如译⑺“ 之美國專利第RE39,484號；Aspar等人之美國專利第 5,374,564號；Aspar等人之美國專利第6,3〇3,468號；Aspar 等人之美國專利第6，；335,258號；Moriceau等人之美國專利 第6,756,286號；Aspar等人之美國專利第6 8〇9 〇44號；及 Aspar等人之美國專利第6,946,365號，該等專利中之每一 者的揭示内容以全文引用之方式併入本文中。 轉移之材料層202"的厚度D2可實質上等於圖2及圖3中所 展示的載體晶圓200内之植入區2〇6的深度D1。在一些實施 例中，轉移之材料層202，，可用作一基底或基板以用於形成 額外器件結構，其中額外器件結構可與經處理之半導體結 構100及經處理之半導體結構400的器件結構電連通。在將 轉移之材料層202"與載體晶圓200拆離後，轉移之材料層 202"的曝露表面可能不合需要地粗糙。舉例而言，轉移之 材料層202"的表面可具有在約一奈米（1 nm)與約2〇奈米（2〇 nm)之間的平均粗糙度。可根據此項技術中已知之技術（諸 如，研磨製程、濕式蝕刻製程及化學機械拋光（CMp)製程 中之一或多者）使轉移之材料層2〇2"的表面平滑至所要程 度，以便促進如下文所描述之進一步處理。因此，轉移之 材料層202"的厚度D2可足以使得能夠將轉移之材料層2〇2" 之一部分移除以實質上使轉移之材料層的表面平滑。舉例 156586.doc •22- 201205688 而言，轉移之材料層202"的厚度D2可在約十奈米（1〇 nm) 與約一千奈米（1000 nm)之間。 在其他實施例中，可（例如）經由一接合製程將一或多個 其他經處理之半導體結構附著至經接合之半導體結構 500，其中該一或多個其他經處理之半導體結構可利用上 文所描述之方法來形成且可與形成於轉移之材料層202"中 及/或轉移之材料層202”之上的額外器件結構電連通並且 與經處理之半導體結構1 00及經處理之半導體結構400的器 件結構電連通。 在其他實施例中，可在使用一各向異性蝕刻製程、一化 學機械拋光製程或其組合處理之後，將轉移之材料層2〇2" 自經接合之半導體結構5〇〇移除。在此實施例中，轉移之 材料層202"的表面粗糙度可能並非一關注點，且轉移之材 料層202可形成為一非常薄之層。舉例而言，轉移之材料 層202"的厚度D2可在約十奈米〇〇 )與約六百奈米 nm)之間。 可在額外處理中再循環及再使用拆離的載體晶圓2〇〇之 材料的剩餘部分202'。 可使用已知設備來使用所揭示之方法，且因此，該等方 法可用於半導體結構之大量製造（HVM)中。因此’所揭示 之方法3使得能夠在日益變薄的半導體結構上製造電子器 件且使得能夠在三維整合式半導體器件之製造期間使器件 結構互連。 本發明之實施例可用於任何一或多種類型之半導體結構 156586.doc -23· 201205688 的二維整合_ ’包括晶粒至晶粒（D2D)整合、晶粒至晶圓 (D2W)、晶圓至晶圓（W2W)整合或此等整合製程之組合。 舉例而言’如圖7中所展示’可將包括複數個個別半導 體晶粒602之半導體晶圓6〇〇單一化以形成單獨的個別晶粒 602。可使用諸如鋸切、雕合與斷裂或雷射切除之技術切 割半導體晶圓600。可識別該複數個半導體晶粒6〇2中的良 裸晶粒。 根據本文中先前所描述之方法，可將自該複數個半導體 晶粒602中所識別的良裸晶粒單獨地及個別地附著至載體 晶粒，並在使用載體晶粒處置良裸晶粒的同時處理（例 如，薄化）良裸晶粒。 參看圖8,接著可根據本文中先前所描述之方法將良裸 晶粒在結構上及電力上耦接至另一晶圓8〇〇。晶圓8〇〇可包 括至少部分地製造於其上之複數個晶粒。舉例而言，良裸 半導體晶粒602之穿晶圓互連件61〇可與晶圓8〇〇上之晶粒 之導電襯墊820對準並接合。可如先前關於圖6所描述執行 一退火製程以沿載體晶粒内之弱化區6〇4拆離載體晶粒之 一部分602·，而同時在良裸晶粒6〇2之穿晶圓互連件61 〇與 晶圓800上之一至少部分形成之晶粒的導電襯墊82〇之間形 成-金屬至金屬接合。在一些實施例中，可使用蝕刻製程 或化學機械拋光製程來移除載體晶粒之剩餘部分6〇2"。在 其他實鉍例中，可將載體晶粒之剩餘部分6〇2"用作一用於 製造額外ϋ件結構之基礎層。在—些實施例中，複數個良 裸晶粒602(晶粒附著至其）可在結構上及電力上耗接至晶圓 156586.doc156586.doc _16_ S 201205688 3〇〇. The carrier wafer 200 can be bonded to the structure 100 for a sufficient amount of time at room temperature or at a high temperature (for example, (100 eC)) and high pressure at a temperature of 10,000 Å. The bonding material u 8 fish 邕 202 or (if present) is bonded to the "conductor material, which can be slid by the non-limiting example of the semiconductor to be processed at about one hundred degrees Celsius (10). 〇 约 约 摄 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及The semiconductor carrier is circumscribed by -r. 叩 仃 - annealing process. In some cases, the processed semiconductor structure 100 is bonded to the carrier wafer 2 without using an adhesive material, which may be The use of the agent to generate the month = reduce or eliminate the pressure limit. The temperature of the further step-by-step processing action generated by the xiao and the bonding of the carrier wafer 2 and the processed semiconductor 100 to form a After the bonded semiconductor structure is 3〇〇, the substrate can be divided into two parts. The major surface (eg, back surface 108) from the processed semiconductor structure (10) is removed to expose the surface of the through-wafer interconnect 116 through the substrate (10). For example, a polishing process, conventional chemical machinery can be used. The polishing process, the anisotropic etch process, or a combination thereof, removes the portion of the substrate 106. In a second embodiment, the substrate 106 can optionally include a etch stop material 120 such as an oxide material (shown in phantom). The surname termination material 120 can be positioned vertically at various locations within the substrate 106. For example, the engraving termination material 120 can be positioned within the substrate 1〇6 above the surface 117 of the through-wafer interconnect 16 , below or at the level of the surface U7. As a non-limiting example, the carrier wafer 2 can be tamped, for example, by 156586.doc -17· 201205688 on the true two fire plate and offset by a rotation. The polishing pad presses the exposed surface of the substrate 106 to perform a polishing and chemical mechanical polishing process to remove portions of the substrate 106 relative to the through-wafer interconnect U6 and the etch stop material 120 (if present) while Chemistry And/or physically active (ie, abrasive) slurry to remove material from substrate 1 。 6. As another non-limiting example, one may include potassium hydroxide (KOH) or tetradecylammonium hydrogen. A solution of oxide (TMAH) is introduced to the exposed surface of substrate ι6 to perform a wet etch process to remove portions of substrate 106 relative to through-wafer interconnect 116 and etch stop material (if present). The wafer 200 is used to dispose of the processed semiconductor structure 1 and provides mechanical support to the processed semiconductor structure 100 during thinning of the substrate 106 to expose the surface of the through-wafer interconnect 16. The remainder of the substrate 106 The portion may have a thickness d2 of about one-half micron (〇·5 μΓη) to about one hundred micrometers (1 μm). As shown in FIG. 3, the bonded semiconductor structure 3 can be inverted in alignment with another processed planar semiconductor structure 400 and contacted with another processed planar semiconductor structure 400, as indicated by directional arrows, for example The exposed surface of the through-wafer interconnect 116 of the bonded semiconductor structure 300 can be contacted with the exposed conductive pad 420 on the active surface 4〇4 of the processed semiconductor structure 400 and bonded to the exposed conductive liner. Pad 42〇. The processed semiconductor structure 4 (similar to the processed semiconductor structure 1) " includes a piece of area 4 〇 2 including the thief structure 410. Device region 4 〇 2 may extend into substrate 406 and extend over and/or over the surface of substrate 406. Substrate 406 can include a substrate as previously described with respect to substrate 106. Similarly, device structure 410 of device region 402 can include device structures as previously described with respect to device structure 11 图 of Figure I56586.doc • 18· 201205688 1 . In some embodiments, the device region 〇2 of the processed semiconductor structure 400 can have a configuration that is at least substantially the same as the device region 丨〇2 of the processed semiconductor structure 100. After forming the device region 4〇2 of the processed semiconductor structure 4, one or more conductive structures (such as conductive pads 420) may be formed over the eraser region 402. The conductive pad 42A may include one or more conductive materials such as one or more metals (eg, copper (CU), aluminum (Ai), tungsten (|), polysilicon, and/or gold (Au), for example, A conductive pad 420 is formed over the processed semiconductor structure 400 in a post-process (BE 〇 L) process. In some embodiments, a conductive material (not shown) can be deposited over the dielectric material 414 and A conductive lining 420 is formed using photolithography techniques to pattern the conductive material to form a conductive pad 42. In other embodiments, the conductive pad 420 can be formed by: depositing a conductive material on the dielectric A plurality of openings (not shown) in the material 414, and performing a chemical mechanical polishing process 2, remove portions of the conductive material overlying the open σ (commonly referred to as "staging process"). The bonded semiconductor structure can be processed and processed by aligning and interfacing the processed semiconductor structure 1 through the wafer interconnect 116 with the conductive substrate 420 of the processed semiconductor structure 4 The semiconductor structures are structurally and electrically coupled to each other. Referring to Figure 6, the processed semiconductor structure 1 can be bonded to the processed semiconductor structure 400 to form another bonded semiconductor structure, wherein the processed semiconductor structure i 〇〇 through the wafer interconnect ii 6 The structure and power loss are connected to the processed semiconductor structure to form a conductive lining 420. The through-wafer interconnect 116 can be directly bonded to the conductive lining in some embodiments using a direct metal-to-metal bonding process such as hot pressing 156586.doc 19 201205688 bonding process, non-thermo-bonding or eutectic bonding process. pad·. For example, the through wafer interconnect 116 and the conductive pad side may each be formed of steel, and the low temperature copper to steel bonding process may be performed by the following operations: the bonded semiconductor structure and the processed semiconductor The structure 40 is exposed to a temperature between about Celsius-Baidu ((10)〇 and about four degrees Celsius (4〇〇.〇) for a sufficient amount of time for bonding the through-wafer interconnect 116 and the conductive pads In other embodiments, the respective processed semiconductor structures can be joined using a direct wafer bonding process! (10) and the active surfaces (10) and 4〇4 (FIG. 5), wherein the active surfaces 108 and 404 can comprise Conductive (eg, metal) regions and non-conductive (eg, dielectric) regions and direct wafer bonding processes simultaneously bonding metal to metal and dielectric to dielectric. One or more of the active surfaces 108 and 404 An optional bonding material is formed over the substrate. As illustrated by the non-limiting example of FIG. 5, an oxide deposition process, such as a low temperature plasma deposition process, can be used to form a (eg) over the substrate 1〇6, for example. Contains dioxide (Si〇2) an optional dielectric bonding material of material 122 (shown in phantom). The optional bonding material 122 may be further planarized to expose the conductive liner 42〇; this planarization may be by chemical mechanical polishing The process is performed. The cerium oxide material 122 can be bonded to the dielectric material 414 of the processed semiconductor structure 400 using an oxide to oxide bonding process, such as the oxide to oxide bonding process described with reference to FIG. For example, the ceria material m can be bonded to the dielectric material 414 at room temperature or at elevated temperatures (eg, at least above one hundred degrees Celsius). The metal to metal bonding process 156586.doc • 20·201205688 and the oxide-to-oxide bonding process can be performed at low temperatures (i.e., temperatures less than about four degrees Celsius (4GGt)), and thus, avoiding damage to the device regions of the processed semiconductor structures 100 and 400. 〇2 and 4〇2. Vertically stacking the processed semiconductor structures HK) and _ after performing the post-process (BE〇L) process in accordance with the method of the present invention enables the processed half during the bonding process A conductive interconnect is formed between the conductor structure 100 and the processed semiconductor structure 4 (eg, via the wafer interconnect 116 and the conductive pad 420). During bonding or bonding of the semiconductor structure 100 to the semiconductor structure 400 Upon completion, one of the materials of the carrier wafer 200, 2〇2, (Fig. 5), may be separated (i.e., detached) from the semiconductor structure 500, leaving the transfer; the material ^2〇2" The processed semiconductor structure 1 can be separated by a portion of the material 202 of the carrier wafer 2 by various chemical, thermal or mechanical processes (such as by a polishing process, an etching process, a polishing process, or For example, s, an executable-single-anneal process is used to bond both semiconductor structures 100 and 40G to each other while the portion of the material of the carrier wafer is 2〇2' and the transferred material layer 2〇2” separation (four), detachment). The annealing process can be performed by the following: the main surface of the processed semiconductor structure (10) (ie, the exposed main surface of the substrate 1 and the exposed surface of the via plug 11) and the processed semiconductor The major surface of the structure 400 (i.e., the exposed major surface of the dielectric material 414 and the exposed surface of the conductive pad 420) is in contact with each other between about two degrees Celsius (2 GG ° C) and about four degrees Celsius (4 GGt ). Annealed at temperature. The annealing process can simultaneously bond both the semiconductor structure 100 and the semiconductor structure 4〇0 (ie, bonding the through-wafer interconnect 116 to the conductive pad 420) and the portions of the carrier wafer 2 Transfer of Semiconductors 156586.doc -21· 201205688 Layer 202" Split. The process known as the SMART-CUTTM process in the industry can be used to separate or detach the portion 202' of material from the transferred material layer 2〇2 " Such processes are described in detail in the following patents: (e.g., U.S. Patent No. RE 39,484, to U.S. Patent No. 5,374,564 to Aspar et al; and U.S. Patent No. 6,3,3,468 to Aspar et al; U.S. Patent No. 6, 335, 258 to Morriceau et al., U.S. Patent No. 6,756,286 to Morriceau et al., U.S. Patent No. 6,8,9,44, to Aspar et al., and U.S. Patent No. 6,946,365 to Aspar et al. The disclosure of each of the patents is incorporated herein by reference in its entirety. The thickness D2 of the transferred material layer 202" can be substantially equal to the implanted area within the carrier wafer 200 shown in Figures 2 and 3. 2D depth D1. In some embodiments, the transferred material layer 202 can be used as a substrate or substrate for forming additional device structures, wherein additional device structures can be processed with the processed semiconductor structure 100 and processed The device structure of the semiconductor structure 400 is in electrical communication. After the transferred material layer 202" is detached from the carrier wafer 200, the exposed surface of the transferred material layer 202" may be undesirably rough. For example, transfer The surface of the material layer 202" may have an average roughness between about one nanometer (1 nm) and about 2 nanometers (2 nanometers). It may be according to techniques known in the art (such as a grinding process, One or more of the wet etching process and the chemical mechanical polishing (CMp) process smoothes the surface of the transferred material layer 2〇2" to the extent necessary to facilitate further processing as described below. Therefore, the transferred material The thickness D2 of the layer 202" may be sufficient to enable removal of a portion of the transferred material layer 2" to substantially smooth the surface of the transferred material layer. For example, 156586.doc • 22-201205688, the transferred material layer The thickness D2 of 202" may be between about ten nanometers (1 〇 nm) and about one thousand nanometers (1000 nm). In other embodiments, one or more other processes may be performed, for example, via a bonding process. The processed semiconductor structure is attached to the bonded semiconductor structure 500, wherein the one or more other processed semiconductor structures can be formed using the methods described above and can be formed in the transferred material layer 202" and/or The additional device structure over the transferred material layer 202" is in electrical communication and is in electrical communication with the processed semiconductor structure 100 and the device structure of the processed semiconductor structure 400. In other embodiments, an anisotropic etch can be used After the process, a chemical mechanical polishing process, or a combination thereof, the transferred material layer 2〇2" is removed from the bonded semiconductor structure 5〇〇. In this embodiment, the surface roughness of the transferred material layer 202" It may not be a concern, and the transferred material layer 202 can be formed as a very thin layer. For example, the transferred material layer 202" thickness D2 can be between about ten nanometers) and about six hundred nanometers nm). The remaining portion 202' of the material of the detached carrier wafer 2 can be recycled and reused in an additional process. The disclosed methods can be used using known devices, and as such, the methods can be used in mass fabrication (HVM) of semiconductor structures. Thus, the disclosed method 3 enables electronic devices to be fabricated on increasingly thinned semiconductor structures and enables device structures to be interconnected during fabrication of three-dimensional integrated semiconductor devices. Embodiments of the present invention can be used for two-dimensional integration of any one or more types of semiconductor structures 156586.doc -23·201205688 _ 'including die-to-die (D2D) integration, die-to-wafer (D2W), wafer To wafer (W2W) integration or a combination of such integration processes. For example, 'shown in FIG. 7' may singulate semiconductor wafers 6 including a plurality of individual semiconductor dies 602 to form individual individual dies 602. The semiconductor wafer 600 can be cut using techniques such as sawing, engraving and breaking or laser ablation. A good die in the plurality of semiconductor dies 6 〇 2 can be identified. The bare die identified from the plurality of semiconductor dies 602 can be individually and individually attached to the carrier die according to the methods previously described herein, and the good die can be disposed of using the carrier die. Simultaneous processing (eg, thinning) of good bare grains. Referring to Figure 8, the good bare die can then be structurally and electrically coupled to another wafer 8 according to the methods previously described herein. The wafer 8 can include a plurality of dies that are at least partially fabricated thereon. For example, the through-wafer interconnect 61 of the good bare semiconductor die 602 can be aligned and bonded to the conductive pads 820 of the die on the wafer 8. An annealing process can be performed as previously described with respect to FIG. 6 to detach one portion of the carrier die 602· along the weakened region 6〇4 within the carrier die while simultaneously interconnecting the wafers in the good die 6〇2 A metal-to-metal bond is formed between the member 61 and the conductive pad 82A of the at least partially formed die on the wafer 800. In some embodiments, an etching process or a chemical mechanical polishing process can be used to remove the remaining portion of the carrier die 6〇2". In other embodiments, the remainder of the carrier die 6〇2" can be used as a base layer for making additional component structures. In some embodiments, a plurality of good die 602 (with die attached thereto) can be structurally and electrically drained to the wafer 156586.doc

S 24· 201205688 800以至少實質上在晶圓8〇〇之上重建構一類似圖7中所展 示之晶圓600的晶圓，且可在單一製程中至少實質上同時 地拆離載體晶粒之部分6〇2·。類似半導體晶圓6〇〇之晶圓的 重建構可包括將良裸晶粒填入晶圓，繼之以氧化物材料之 沈積及平坦化，以形成良裸晶粒嵌入於氧化物材料内之連 續表面。 下文描述本發明之額外實例非限制性實施例。 實施例1 : 一種製造半導體結構之方法，其包含：在第 基板上形成一包括積體電路之至少一部分的第一半導體 結構；將離子植人至—載體晶圓+以在載體晶圓内形成一 弱化區域；將載體晶圓直接接合至第一半導體結構之第一 側；在將載體晶圓附著至第一半導體的同時使用用以處置 第一半導體結構之載體晶圓處理第一半導體結構；將包括 一積體電路之至少一部分的第二半導體結構直接接合至第 一半導體結構之第二側，第一半導體結構之第二側與載體 晶圓直接接合至的半導體結構之第一側對置；及將一來自 載體晶圓之材料層沿載體晶圓中之弱化區域與載體晶圓之 剩餘部分分離。 實施例2:如實施例丨之方法’其進一步包含形成至少部 分地延伸穿過第一基板之至少一穿晶圓互連件（twi)。 實施例3 :如實施例丨或實施例2之方法，其中處理第一 半導體結構包含將第-基板之—部分自第_半導體結構之 第二側移除且曝露第一半導體結構之積體電路的該至少一 部分之至少一導電結構。 156586.doc -25- 201205688 實施例4:如實施例3之方法，其中曝露第一半導體結構 之積體電路的該至少一部分之至少一導電結構包含曝露第 一半導體結構中之一穿晶圓互連件（twi)。 實施例5 .如實施例4之方法，其中將第二半導體結構直 接接合至第一半導體結構之第二側包含將第一半導體結構 之穿晶圓互連件直接接合至第二半導體結構之至少一導電 元件。 實施例6 :如實施例1至5中任一項之方法，其中將第二 半導體結構直接接合至第一半導體結構之第二側包含將第 一半導體結構之至少一導電元件的金屬直接接合至第二半 導體結構之至少一導電元件的金屬。 實施例7 ··如實施例1至6令任一項之方法，其甲將第二 半導體結構直接接合至第一半導體結構之第二側包含將第 二半導體結構之半導體材料及氧化物材料中之至少一者直 接接合至第一半導體結構之半導體材料及氧化物材料中之 至少一者。 實施例8:如實施例丨至7中任一項之方法’其中將載體 晶圓之材料層沿載體晶圓中之弱化區域與載體晶圓之剩餘 部分分離包含使載體晶圓在至少100t：之溫度下退火，且 將上覆弱化區域之載體晶圓之一部分與仍附著至第一半導 體結構之載體晶圓之另一部分拆離。 實施例9:如實施例1至8中任一項之方法，其中將材料 層沿弱化區域與載體晶圓分離包含留下具有約1〇 nm與約 1000 urn之間之厚度的載體基板之材料層附著至第一半導 156586.doc •26· 201205688 體結構。 實施例10:如實施例1至9中任一項之方法，其中第二肀 導體結構至第一半導體結構之第二側之直接接合導致材料 層沿載體晶圓中之弱化區域與載體晶圓之分離。 實施例11 :如實施例10之方法，其中將載體晶圓直接接 合至第半導體結構之第一側包含在不沿載體晶圓中之弱 化區域劃为載體晶圓之情況下使載體晶圓沿載體晶圓中之 弱化區域弱化。 實施例12 : —種製造半導體結構之方法，其包含：將離 子植入至一第一半導體結構中且在該第一半導體結構中形 成一弱化區域；將該第一半導體結構之表面直接接合至第 二半導體結構之表面以形成一包括第一半導體結構及第二 半導體結構的經接合之半導體結構；在移除第二半導體結 構之一部分並曝露至少部分地延伸穿過第二半導體結構之 至少一導電結構的同時’使用第一半導體結構處置經接合 之半導體結構；將穿過第二半導體結構曝露之該至少一導 電結構與第三半導體結構之至少一導電結構對準；加熱經 接合之半導體結構及第三半導體結構；回應於加熱經接合 之半導體結構及第三半導體結構而將穿過第二半導體結構 曝露的該至少一導電結構直接接合至第三半導體結構之該 至少一導電結構；及回應於加熱經接合之半導體結構及第 三半導體結構而沿弱化區域劃分第一半導體結構並將第一 半導體結構之一部分留在第二半導體結構上。 實施例13 :如實施例12之方法，其進一步包含形成穿過 156586.doc -27- 201205688 第二半導體結構曝露的該至少一導電結構以包含一穿晶圓 互連件（TWI)。 實施例14 :如實施例12或實施例13之方法，其中將離子 植入至第一半導體結構中包含將半導體晶圓之表面曝露至 1〇16離子數/cm2與2xl017離子數/cm2之間的劑量及1〇 Kev 與150 KeV之間的能量的離子。 實施例I5 ··如實施例12至丨4中任一項之方法，其中將離 子植入至第一半導體結構中包含將離子植入至載體晶圓中 且在載體晶圓内在距載體晶圓之一平坦主表面約1〇⑽與 約1000 nm之間的深度處形成一弱化區域。 實施例16 :如實施例12至15中任一項之方法，其中將第 一半導體結構之表面直接接合至第二半導體結構之表面以 形成經接合之半導體結構包含將一矽載體晶圓之表面接合 至第二半導體結構之矽或二氧化矽材料之表面。 σ 實施例17:如實施例12至16中任一項之方法其中將第 一半導體結構之表面直接接合至第二半導體結構之表面以 形成經接合之半導體結構包含將一矽載體晶圓上之二氧化 石夕材料之表面接合至第二半導體結構之⑪或二氧切 之表面。 — 實施例18 :如實施例12至17中任一項之方法，其中將穿 過第二半導體結構曝露的該至少一導電結構與—第三半導 體結構之至少-導電結構對準包含將穿過第二半導體結構 曝露之至少一銅穿晶圓互連件（TWI)與第三半導體結構之 至少一銅接合襯墊對準。 156586.docS 24· 201205688 800 reconstitutes a wafer similar to the wafer 600 shown in FIG. 7 at least substantially above the wafer 8 and can detach the carrier die at least substantially simultaneously in a single process The part is 6〇2·. A reconstruction of a wafer similar to a semiconductor wafer may include filling a good bare die into a wafer, followed by deposition and planarization of an oxide material to form a good bare die embedded in the oxide material. Continuous surface. Additional example non-limiting embodiments of the invention are described below. Embodiment 1 : A method of fabricating a semiconductor structure, comprising: forming a first semiconductor structure including at least a portion of an integrated circuit on a substrate; implanting ions into a carrier wafer + to form in a carrier wafer a weakened region; directly bonding the carrier wafer to the first side of the first semiconductor structure; processing the first semiconductor structure using the carrier wafer for processing the first semiconductor structure while attaching the carrier wafer to the first semiconductor; Bonding a second semiconductor structure including at least a portion of an integrated circuit directly to a second side of the first semiconductor structure, the second side of the first semiconductor structure being opposite the first side of the semiconductor structure to which the carrier wafer is directly bonded And separating a layer of material from the carrier wafer along the weakened region of the carrier wafer from the remainder of the carrier wafer. Embodiment 2: The method of Embodiment </ RTI> further comprising forming at least one through wafer interconnect (twi) extending at least partially through the first substrate. Embodiment 3: The method of Embodiment 2 or Embodiment 2, wherein processing the first semiconductor structure comprises removing the first substrate from the second side of the first semiconductor structure and exposing the first semiconductor structure At least one portion of the at least one electrically conductive structure. The method of embodiment 3, wherein the at least one conductive structure exposing the at least one portion of the integrated circuit of the first semiconductor structure comprises exposing one of the first semiconductor structures to the wafer Connected pieces (twi). The method of embodiment 4, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises bonding the through-wafer interconnect of the first semiconductor structure directly to the second semiconductor structure A conductive element. The method of any one of embodiments 1 to 5, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding the metal of the at least one conductive element of the first semiconductor structure to a metal of at least one conductive element of the second semiconductor structure. The method of any one of embodiments 1 to 6, wherein the bonding of the second semiconductor structure directly to the second side of the first semiconductor structure comprises the semiconductor material and the oxide material of the second semiconductor structure At least one of the two is directly bonded to at least one of a semiconductor material and an oxide material of the first semiconductor structure. Embodiment 8: The method of any one of Embodiments to 7 wherein the material layer of the carrier wafer is separated from the remaining portion of the carrier wafer along the weakened region of the carrier wafer to comprise the carrier wafer at least 100t: Annealing at a temperature and detaching a portion of the carrier wafer overlying the weakened region from another portion of the carrier wafer still attached to the first semiconductor structure. The method of any one of embodiments 1 to 8, wherein separating the layer of material from the carrier wafer along the weakened region comprises leaving a material of the carrier substrate having a thickness between about 1 〇 nm and about 1000 urn The layer is attached to the first semi-conductor 156586.doc •26·201205688 Body structure. The method of any one of embodiments 1 to 9, wherein the direct bonding of the second germanium conductor structure to the second side of the first semiconductor structure results in a weakened region of the material layer along the carrier wafer and the carrier wafer Separation. Embodiment 11: The method of Embodiment 10, wherein directly bonding the carrier wafer to the first side of the semiconductor structure comprises causing the carrier wafer edge to be formed without forming a weakened region in the carrier wafer as a carrier wafer The weakened area in the carrier wafer is weakened. Embodiment 12: A method of fabricating a semiconductor structure, comprising: implanting ions into a first semiconductor structure and forming a weakened region in the first semiconductor structure; bonding the surface of the first semiconductor structure directly to a surface of the second semiconductor structure to form a bonded semiconductor structure including the first semiconductor structure and the second semiconductor structure; removing at least one portion of the second semiconductor structure and exposing at least partially extending through the second semiconductor structure Simultaneously using the first semiconductor structure to dispose the bonded semiconductor structure; aligning the at least one electrically conductive structure exposed through the second semiconductor structure with at least one electrically conductive structure of the third semiconductor structure; heating the bonded semiconductor structure And the third semiconductor structure; directly bonding the at least one conductive structure exposed through the second semiconductor structure to the at least one conductive structure of the third semiconductor structure in response to heating the bonded semiconductor structure and the third semiconductor structure; and responding Heating the bonded semiconductor structure and the third semiconductor junction A first semiconductor structure along the weakened region and the remaining portion of the first division of the semiconductor structure on the second semiconductor structure. Embodiment 13: The method of Embodiment 12, further comprising forming the at least one electrically conductive structure exposed through the second semiconductor structure of 156586.doc -27-201205688 to include a through-wafer interconnect (TWI). Embodiment 14: The method of Embodiment 12 or Embodiment 13, wherein implanting ions into the first semiconductor structure comprises exposing the surface of the semiconductor wafer to between 1 〇 16 ions/cm 2 and 2 x 10 17 ions/cm 2 The dose of ions and energy between 1 〇 Kev and 150 KeV. The method of any one of embodiments 12 to 4, wherein implanting ions into the first semiconductor structure comprises implanting ions into the carrier wafer and within the carrier wafer from the carrier wafer A flat main surface forms a weakened region at a depth of between about 1 〇 (10) and about 1000 nm. The method of any one of embodiments 12 to 15, wherein the surface of the first semiconductor structure is directly bonded to the surface of the second semiconductor structure to form a bonded semiconductor structure comprising a surface of a carrier wafer Bonded to the surface of the tantalum or ceria material of the second semiconductor structure. The method of any one of embodiments 12 to 16 wherein the surface of the first semiconductor structure is directly bonded to the surface of the second semiconductor structure to form a bonded semiconductor structure comprising a germanium carrier wafer The surface of the dioxide dioxide material is bonded to the surface of the second semiconductor structure 11 or dioxo prior. The method of any one of embodiments 12 to 17, wherein aligning the at least one electrically conductive structure exposed through the second semiconductor structure with the at least one electrically conductive structure of the third semiconductor structure comprises passing through At least one copper through wafer interconnect (TWI) exposed by the second semiconductor structure is aligned with at least one copper bond pad of the third semiconductor structure. 156586.doc

S • 28 · 201205688 實施例19 :如實施例18之方法，其中加熱經接合之半導 體結構及第三半導體結構包含將經接合之半導體結構及第 三半導體結構加熱至在約l〇(TC與約4〇〇它之間的溫度。 實施例20 :如實施例12至19中任一項之方法，其進一步 包含在沿弱化區域劃分第一半導體結構之後處理第二半導 體結構上的第一半導體結構之部分，且在第二半導體結構 上的第一半導體結構之該部分上或該部分中形成至 件結構。 實施例21 :如實施例12至19_任一項之方法，其進一步 包含在沿弱化區域劃分第一半導體結構之後將第_半導體 結構之部分自第二半導體結構移除。 實施例22: -種經接合之半導體結構，丨包含：複數個 經接合之經處理之半導體結構；及—載體晶粒或晶圓，該 載體晶粒或晶圓接合至該複數個經接合之經處理之半導體 結構中的至少-經處理之半導體結構，該載體晶粒或晶圓 具有一弱化區，該弱化區中包含複數個植入離子，該複數 個植入離子係在距接合至該複數個經接合之經處理之半導 體結構中的該至少一經處理之半導體結構的載體晶粒或晶 圓之一表面10 nm與1〇〇〇 nm之間的平均深度處。 實施例23 ··如實施例22之經接合之半導體結構，其中該 複數個經接合之經處理之半導體結構至少部分地藉由穿晶 圓互連件而在結構上及電力上耦接在一起。 實施例24 :如實施例22或23之經接合之半導體結構，其 中該複數個經接合之經處理之半導體結構在其之間不使用 156586.doc -29· 201205688 黏著材料的情況下直接接合在一起。 實施例25 :如實施例22至24中任一項之經接合之半導體 結構’其中載體晶粒或晶圓直接接合至該複數個經接合之 經處理之半導體結構中的該至少一經處理之半導體結構。 雖然本文中已使用特定實例描述本發明之實施例，但一 般熟習此項技術者將認識到並瞭解，本發明不限於實例實 施例之細節。實情為，可在不偏離如下文所主張的本發明 之範嘴的情況下對實例實施例作出許多添加、刪除及修 改°舉例而言’來自一實施例之特徵可與其他實施例之特 徵組合，同時仍包含於如發明者所預期的本發明之範疇 内0 【圖式簡單說明】 圖1為包括穿晶圓互連件之經處理之半導體結構的示意 性橫截面圖； 圖2為經接合之半導體結構的示意性橫截面圖，該經接 &amp;之半導體結構包括根據本發明之方法之實施例而直接接 a至包含一載體晶圓之另一半導體結構的圖1之經處理之 半導體結構； 圖3為在接合至經處理之半導體結構之前的圖2中所展示 之載體晶圓的示意性橫截面圖； 圖4為在使用載體晶圓處置經處理之半導體結構的同時 使、’星處理之半導體結構薄化之後的圖2之經接合之半導體 結構的示意性橫戴面圖； 圖5為圖4中所展示的經接合之半導體結構的示意性橫截 156586.doc 201205688 χ;接&amp;之半導體結構反轉並與經接合之半導體結 構可根據本發明之方法之實施例而附著至的另—經處理之 半導體結構對準； 圖6為可藉由將圖5中所展示的經對準之半導體結構接合 I而形成的經接合之半導體結構的示意性橫截面圖， 進步說明在將半導體結構接合在一起之後的载體晶圓 之劃分； 圖7為可根據本發明之方法之實施例形成的三維半導體 結構的示意性橫截面圖；及 圖8為一半導體結構之示意性橫截面圖且用以說明包括 在一維（3D)整合製程中將個別半導體晶粒接合至相對較大 之半導體晶圓上的本發明之方法之實施例。 【主要元件符號說明】 100 經處理之半導體結構 102 器件區域 104 作用表面 106 基板 108 背表面/作用表面 110 器件結構/介層孔插塞 114 介電材料 116 穿晶圓互連件 117 表面 118 接合材料 120 蝕刻終止材料 I56586.doc -31 · 201205688 122 二氧化矽（si〇2)材料/接合材料 200 載體晶圓 202 半導體材料 202' 載體晶圓之材料之一部分 202&quot; 轉移之材料層 204 轉移區域 206 植區 218 接合材料 300 經接合之半導體結構 400 經處理之平坦半導體結構/經處理之半導體結構 402 器件區域 404 作用表面 406 基板 410 器件結構 414 介電材料 420 導電襯墊 500 經接合之半導體結構 600 半導體晶圓 602 半導體晶粒 602， 載體晶粒之一部分 602&quot; 載體晶粒之剩餘部分 604 弱化區 610 穿晶圓互連件 800 晶固 820 導電襯墊 156586.doc -32- sThe method of embodiment 18, wherein heating the bonded semiconductor structure and the third semiconductor structure comprises heating the bonded semiconductor structure and the third semiconductor structure to about 1 〇 (TC and about The method of any one of embodiments 12 to 19, further comprising processing the first semiconductor structure on the second semiconductor structure after dividing the first semiconductor structure along the weakened region And a portion of the first semiconductor structure on the second semiconductor structure is formed on the portion of the first semiconductor structure or in the portion. Embodiment 21: The method of any one of embodiments 12 to 19, further comprising The weakened region divides a portion of the first semiconductor structure from the second semiconductor structure after the first semiconductor structure is divided. Embodiment 22: a bonded semiconductor structure, the germanium comprising: a plurality of bonded processed semiconductor structures; a carrier die or wafer bonded to at least a processed semiconductor junction of the plurality of bonded processed semiconductor structures The carrier die or wafer has a weakened region, the weakened region comprising a plurality of implanted ions, the plurality of implanted ions being at least from the bonded to the plurality of bonded processed semiconductor structures The surface of one of the carrier dies or wafers of the processed semiconductor structure at an average depth between 10 nm and 1 〇〇〇 nm. Embodiment 23 The bonded semiconductor structure of Embodiment 22, wherein the plurality of semiconductor structures The bonded semiconductor structures are structurally and electrically coupled together at least in part by a through-wafer interconnect. Embodiment 24: The bonded semiconductor structure of embodiment 22 or 23, wherein A plurality of bonded processed semiconductor structures are directly joined together without the use of an adhesive material 156586.doc -29 201205688. Embodiment 25: Bonded as in any of embodiments 22-24 a semiconductor structure 'where the carrier die or wafer is directly bonded to the at least one processed semiconductor structure of the plurality of bonded processed semiconductor structures. Although specific to the use herein The embodiments of the present invention are described by way of example, but those skilled in the art will recognize and appreciate that the invention is not limited to the details of the example embodiments. In fact, the present invention may be practiced without departing from the scope of the invention as claimed Many additions, deletions, and modifications are made to the example embodiments. For example, features from one embodiment may be combined with features of other embodiments while still being included within the scope of the invention as contemplated by the inventors. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a processed semiconductor structure including a through-wafer interconnect; FIG. 2 is a schematic cross-sectional view of a bonded semiconductor structure, the bonded semiconductor structure Included in accordance with an embodiment of the method of the present invention, a semiconductor structure of FIG. 1 directly coupled to another semiconductor structure including a carrier wafer; FIG. 3 is in FIG. 2 prior to bonding to the processed semiconductor structure. A schematic cross-sectional view of a carrier wafer as shown; FIG. 4 is a semiconductor structure for the treatment of a processed semiconductor structure while using a carrier wafer Figure 2 is a schematic cross-sectional view of the bonded semiconductor structure of Figure 2; Figure 5 is a schematic cross-section of the bonded semiconductor structure shown in Figure 4 156586.doc 201205688 χ; Inverted and aligned with the bonded semiconductor structure to which another processed semiconductor structure is attached in accordance with an embodiment of the method of the present invention; FIG. 6 is an aligned semiconductor that can be illustrated by FIG. A schematic cross-sectional view of a bonded semiconductor structure formed by structural bonding I, an advancement illustrating the division of the carrier wafer after bonding the semiconductor structures together; FIG. 7 is an embodiment that can be formed in accordance with an embodiment of the method of the present invention A schematic cross-sectional view of a three-dimensional semiconductor structure; and FIG. 8 is a schematic cross-sectional view of a semiconductor structure for illustrating bonding of individual semiconductor dies to relatively large semiconductor crystals in a one-dimensional (3D) integration process An embodiment of the method of the invention on a circle. [Major component symbol description] 100 Processed semiconductor structure 102 Device region 104 Active surface 106 Substrate 108 Back surface / active surface 110 Device structure / via plug 114 Dielectric material 116 Through wafer interconnect 117 Surface 118 Bonding Material 120 Etch Stop Material I56586.doc -31 · 201205688 122 Cerium Oxide (Si〇2) Material/Join Material 200 Carrier Wafer 202 Semiconductor Material 202' One of the Materials of the Carrier Wafer 202&quot; Transfer Material Layer 204 Transfer Area 206 implanted region 218 bonding material 300 bonded semiconductor structure 400 processed planar semiconductor structure / processed semiconductor structure 402 device region 404 active surface 406 substrate 410 device structure 414 dielectric material 420 conductive pad 500 bonded semiconductor structure 600 semiconductor wafer 602 semiconductor die 602, one portion of carrier die 602 &quot; remaining portion of carrier die 604 weakened region 610 through wafer interconnect 800 crystal solid 820 conductive pad 156586.doc -32- s

Claims (1)

201205688 七、申請專利範圍： 1. 一種製造半導體結構之方法，其包含： 在第一基板上形成包括積體電路之至少一部分的第一 半導體結構； 將離子植入至載體晶圓中以在該載體晶圓内形成一弱 化區域， 將該載體晶圓直接接合至該第一半導體結構之第一 側； 在將該載體晶圓附著至該第一半導體結構的同時，使 用用以處置該第一半導體結構之該載體晶圓處理該第一 半導體結構； 將包括積體電路之至少一部分的第二半導體結構直接 接合至該第一半導體結構之第二側，該第一半導體結構 之該第二側係與該載體晶圓直接接合的該半導體結構之 該第--側對置；及 -_來自該載體晶圓之材料層沿該載體晶圓中之該弱 化區域與該載體晶圓之剩餘部分分離。 項1之方法，其進一步包含形成至少部分地延 穿過該第一基板之至少一穿晶圓互連件（TWI)。 3.如明求項1之方法，其中處理該第 該第—美干等媸、構包含將 土板之一部分自該第一半 除，且曝露兮莖牛導祖結構之该第二側移 h路β第一半導體姓播夕4_ 部分的至少道Μ 積體電路之該至少一 ^ J 一導電結構。 4·如請求項3之方法，盆由s恭 、。、露該第—半導體結構之該積 156586.doc 201205688 體電路之該至少一部分的至少一導電結構包含曝露該第 一半導體結構中之一穿晶圓互連件（TWI)。 5. 如清求項4之方法，其中將該第二半導體結構直接接合 至6亥第一半導體結構之該第二側包含將該第一半導體結 構之該穿晶圓互連件直接接合至該第二半導體結構之至 少一導電元件。 6. 如清求項1之方法，其中將該第二半導體結構直接接合 至该第一半導體結構之該第二側包含將該第一半導體結 構之至少一導電元件之金屬直接接合至該第二半導體結 構之至少一導電元件之金屬。 7. 如請求項1之方法，其中將該第二半導體結構直接接合 至s亥第一半導體結構之該第二側包含將該第二半導體結 構之半導體材料及氧化物材料中之至少一者直接接合至 °亥第半導體結構之半導體材料及氧化物材料中之至少 一者。 8. 如請求項1之方法’其中將該載體晶圓之該材料層沿該 載體晶圓中之該弱化區域與該載體晶圓之剩餘部分分離 包含使該載體晶圓在至少1 〇〇°C之溫度下退火，且將上 覆該弱化區域之該載體晶圓之一部分自該載體晶圓之仍 附著至該第一半導體結構之另一部分拆離。 9. 如請求項1之方法’其中將該材料層沿該弱化區域自該 載體晶圓分離包含留下具有在約1〇 nrn與約1〇〇〇 nm之間 之厚度的該載體晶圓之材料層附著至該第一半導體結 構。 156586d〇C -2- S 201205688 1 〇·如請求項1之方法，其中該第二半導體結構至該第一半 導體結構之該第二側的該直接接合導致該材料層沿該載 體晶圓中之該弱化區域與該載體晶圓分離。 11. 如請求項1 〇之方法，其中該載體晶圓至該第一半導體結 構之該第一側的該直接接合包含在不沿該載體晶圓中之 該弱化區域劃分該載體晶圓之情況下使該載體晶圓沿該 載體晶圓中之該弱化區域弱化。 12. —種經接合之半導體結構，其包含： 複數個經接合之經處理之半導體結構；及 一載體晶粒或晶圓，其接合至該複數個經接合之經處 理之半導體結構中的至少一經處理之半導體結構，該載 體ΒΘ粒或晶圓具有一弱化區，該弱化區中包含複數個植 入離子’該複數個植入離子係在距接合至該複數個經接 合之經處理之半導體結構中的該至少一經處理之半導體 結構的該載體晶粒或晶圓之一表面丨〇 ]1111與丨〇〇〇 nm之間 的平均深度處。 13. 如請求項12之經接合之半導體結構，其中該複數個經接 合之經處理之半導體結構至少部分地藉由穿晶圓互連件 而在結構上及電力上耦接在一起。 14. 如請求項12之經接合之半導體結構’其中該複數個經接 合之經處理之半導體結構係在其間不使用黏著材料之情 況下直接接合在一起。 15. 如請求項Η之經接合之半導體結構，其中該載體晶粒或 晶圓係直接接合至該複數個經接合之經處理之半導體結 構中的該至少一經處理之半導體結構。 156586.doc201205688 VII. Patent Application Range: 1. A method of fabricating a semiconductor structure, comprising: forming a first semiconductor structure including at least a portion of an integrated circuit on a first substrate; implanting ions into the carrier wafer to Forming a weakened region in the carrier wafer, directly bonding the carrier wafer to the first side of the first semiconductor structure; and using the carrier wafer to the first semiconductor structure while using the first semiconductor structure The carrier wafer of the semiconductor structure processes the first semiconductor structure; directly bonding a second semiconductor structure including at least a portion of the integrated circuit to a second side of the first semiconductor structure, the second side of the first semiconductor structure The first side of the semiconductor structure directly bonded to the carrier wafer; and - the material layer from the carrier wafer along the weakened area of the carrier wafer and the remainder of the carrier wafer Separation. The method of clause 1, further comprising forming at least one through wafer interconnect (TWI) extending at least partially through the first substrate. 3. The method of claim 1, wherein the processing of the first smear, the scorpion, comprises removing a portion of the soil plate from the first half and exposing the second lateral movement of the stalk stalk structure The at least one of the at least one of the circuit circuits of the h-channel β first semiconductor surname and the fourth semiconductor portion is electrically conductive. 4. According to the method of claim 3, the basin is s. The at least one electrically conductive structure of the at least one portion of the bulk circuit includes exposing one of the first semiconductor structures to a through-wafer interconnect (TWI). 5. The method of claim 4, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding the through-wafer interconnect of the first semiconductor structure to the At least one electrically conductive element of the second semiconductor structure. 6. The method of claim 1, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding a metal of the at least one conductive element of the first semiconductor structure to the second a metal of at least one electrically conductive element of the semiconductor structure. 7. The method of claim 1, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directing at least one of a semiconductor material and an oxide material of the second semiconductor structure Bonding to at least one of a semiconductor material and an oxide material of the semiconductor structure. 8. The method of claim 1 wherein the material layer of the carrier wafer is separated from the remaining portion of the carrier wafer along the weakened region of the carrier wafer such that the carrier wafer is at least 1 〇〇° An annealing is performed at a temperature of C, and a portion of the carrier wafer overlying the weakened region is detached from another portion of the carrier wafer that is still attached to the first semiconductor structure. 9. The method of claim 1 wherein separating the layer of material from the carrier wafer along the weakened region comprises leaving the carrier wafer having a thickness between about 1 〇 nrn and about 1 〇〇〇 nm. A layer of material is attached to the first semiconductor structure. The method of claim 1, wherein the direct bonding of the second semiconductor structure to the second side of the first semiconductor structure results in the material layer being in the carrier wafer The weakened region is separated from the carrier wafer. 11. The method of claim 1, wherein the direct bonding of the carrier wafer to the first side of the first semiconductor structure comprises dividing the carrier wafer without the weakened region in the carrier wafer The carrier wafer is weakened along the weakened region in the carrier wafer. 12. A bonded semiconductor structure comprising: a plurality of bonded processed semiconductor structures; and a carrier die or wafer bonded to at least the plurality of bonded processed semiconductor structures In a processed semiconductor structure, the carrier particle or wafer has a weakened region comprising a plurality of implanted ions, the plurality of implanted ions being bonded to the plurality of bonded processed semiconductors The surface of the carrier die or wafer of the at least one processed semiconductor structure in the structure is at an average depth between 1111 and 丨〇〇〇nm. 13. The bonded semiconductor structure of claim 12, wherein the plurality of bonded processed semiconductor structures are structurally and electrically coupled together at least in part by a through-wafer interconnect. 14. The bonded semiconductor structure of claim 12 wherein the plurality of bonded semiconductor structures are directly bonded together without the use of an adhesive material therebetween. 15. The bonded semiconductor structure of claim 1, wherein the carrier die or wafer is bonded directly to the at least one processed semiconductor structure of the plurality of bonded processed semiconductor structures. 156586.doc
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TWI445101B (en) 2014-07-11
KR101311332B1 (en) 2013-09-27
KR20120010120A (en) 2012-02-02
CN105489512A (en) 2016-04-13
CN105489512B (en) 2018-01-30
CN102339769A (en) 2012-02-01

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