KR101167624B1 - 피에칭재의 플라즈마 에칭방법 - Google Patents

피에칭재의 플라즈마 에칭방법 Download PDF

Info

Publication number
KR101167624B1
KR101167624B1 KR1020090069388A KR20090069388A KR101167624B1 KR 101167624 B1 KR101167624 B1 KR 101167624B1 KR 1020090069388 A KR1020090069388 A KR 1020090069388A KR 20090069388 A KR20090069388 A KR 20090069388A KR 101167624 B1 KR101167624 B1 KR 101167624B1
Authority
KR
South Korea
Prior art keywords
etching
mask
target material
opening
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020090069388A
Other languages
English (en)
Korean (ko)
Other versions
KR20100126149A (ko
Inventor
마사토시 미야케
노부유키 네기시
마사토시 오야마
다다미츠 가네키요
마사루 이자와
Original Assignee
가부시키가이샤 히다치 하이테크놀로지즈
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 히다치 하이테크놀로지즈 filed Critical 가부시키가이샤 히다치 하이테크놀로지즈
Publication of KR20100126149A publication Critical patent/KR20100126149A/ko
Application granted granted Critical
Publication of KR101167624B1 publication Critical patent/KR101167624B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
KR1020090069388A 2009-05-22 2009-07-29 피에칭재의 플라즈마 에칭방법 Expired - Fee Related KR101167624B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009124508A JP2010272758A (ja) 2009-05-22 2009-05-22 被エッチング材のプラズマエッチング方法
JPJP-P-2009-124508 2009-05-22

Publications (2)

Publication Number Publication Date
KR20100126149A KR20100126149A (ko) 2010-12-01
KR101167624B1 true KR101167624B1 (ko) 2012-07-20

Family

ID=43124841

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090069388A Expired - Fee Related KR101167624B1 (ko) 2009-05-22 2009-07-29 피에칭재의 플라즈마 에칭방법

Country Status (4)

Country Link
US (1) US20100297849A1 (enExample)
JP (1) JP2010272758A (enExample)
KR (1) KR101167624B1 (enExample)
TW (1) TW201042719A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9039909B2 (en) * 2011-02-28 2015-05-26 Tokyo Electron Limited Plasma etching method, semiconductor device manufacturing method and computer-readable storage medium
US8679358B2 (en) * 2011-03-03 2014-03-25 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
JP6085079B2 (ja) * 2011-03-28 2017-02-22 東京エレクトロン株式会社 パターン形成方法、処理容器内の部材の温度制御方法、及び基板処理システム
US8598040B2 (en) * 2011-09-06 2013-12-03 Lam Research Corporation ETCH process for 3D flash structures
US8703619B2 (en) 2012-01-19 2014-04-22 Headway Technologies, Inc. Taper-etching method and method of manufacturing near-field light generator
US8975185B2 (en) * 2012-11-26 2015-03-10 Spansion, Llc Forming charge trap separation in a flash memory semiconductor device
JP2014225501A (ja) * 2013-05-15 2014-12-04 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
JP6396699B2 (ja) * 2014-02-24 2018-09-26 東京エレクトロン株式会社 エッチング方法
JP6339963B2 (ja) * 2015-04-06 2018-06-06 東京エレクトロン株式会社 エッチング方法
US9934984B2 (en) 2015-09-09 2018-04-03 International Business Machines Corporation Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication
CN106548933B (zh) * 2015-09-23 2020-07-17 北京北方华创微电子装备有限公司 一种刻蚀工艺
JP2018046185A (ja) * 2016-09-15 2018-03-22 東京エレクトロン株式会社 酸化シリコン及び窒化シリコンを互いに選択的にエッチングする方法
US10775323B2 (en) * 2016-10-18 2020-09-15 Kla-Tencor Corporation Full beam metrology for X-ray scatterometry systems
JP2020141033A (ja) * 2019-02-27 2020-09-03 東京エレクトロン株式会社 堆積処理方法及びプラズマ処理装置
JP7721458B2 (ja) * 2022-02-21 2025-08-12 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理システム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158306A (ja) * 2005-11-11 2007-06-21 Elpida Memory Inc 半導体集積回路装置の製造方法
WO2008038751A1 (en) * 2006-09-28 2008-04-03 Nikon Corporation Line width measuring method, image forming status detecting method, adjusting method, exposure method and device manufacturing method

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
JP3018532B2 (ja) * 1991-02-26 2000-03-13 ソニー株式会社 ドライエッチング方法
JP3024317B2 (ja) * 1991-10-25 2000-03-21 日本電気株式会社 半導体装置の製造方法
JP2884970B2 (ja) * 1992-11-18 1999-04-19 株式会社デンソー 半導体のドライエッチング方法
US5605603A (en) * 1995-03-29 1997-02-25 International Business Machines Corporation Deep trench process
JP3351183B2 (ja) * 1995-06-19 2002-11-25 株式会社デンソー シリコン基板のドライエッチング方法及びトレンチ形成方法
US6127278A (en) * 1997-06-02 2000-10-03 Applied Materials, Inc. Etch process for forming high aspect ratio trenched in silicon
US6242788B1 (en) * 1997-08-01 2001-06-05 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6159862A (en) * 1997-12-27 2000-12-12 Tokyo Electron Ltd. Semiconductor processing method and system using C5 F8
JPH11307512A (ja) * 1998-04-23 1999-11-05 Sony Corp エッチング方法
WO1999067817A1 (en) * 1998-06-22 1999-12-29 Applied Materials, Inc. Silicon trench etching using silicon-containing precursors to reduce or avoid mask erosion
JP2001110784A (ja) * 1999-10-12 2001-04-20 Hitachi Ltd プラズマ処理装置および処理方法
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist
US6451705B1 (en) * 2000-08-31 2002-09-17 Micron Technology, Inc. Self-aligned PECVD etch mask
JP2002110647A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
JP2002289592A (ja) * 2001-03-28 2002-10-04 Sony Corp 半導体装置の製造方法
US20020142610A1 (en) * 2001-03-30 2002-10-03 Ting Chien Plasma etching of dielectric layer with selectivity to stop layer
US6743727B2 (en) * 2001-06-05 2004-06-01 International Business Machines Corporation Method of etching high aspect ratio openings
JP2003023000A (ja) * 2001-07-11 2003-01-24 Hitachi Ltd 半導体装置の製造方法
KR100430472B1 (ko) * 2001-07-12 2004-05-10 삼성전자주식회사 듀얼 다마신 공정을 이용한 배선 형성 방법
US20030082838A1 (en) * 2001-10-26 2003-05-01 Joseph Petrucci Method and system for monitoring a semiconductor wafer plasma etch process
KR100550640B1 (ko) * 2001-11-30 2006-02-09 주식회사 하이닉스반도체 불화아르곤 노광원을 이용한 패턴 형성 방법
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US7074723B2 (en) * 2002-08-02 2006-07-11 Applied Materials, Inc. Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system
US7169695B2 (en) * 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
US6833325B2 (en) * 2002-10-11 2004-12-21 Lam Research Corporation Method for plasma etching performance enhancement
US6916746B1 (en) * 2003-04-09 2005-07-12 Lam Research Corporation Method for plasma etching using periodic modulation of gas chemistry
US6893938B2 (en) * 2003-04-21 2005-05-17 Infineon Technologies Ag STI formation for vertical and planar transistors
JP4564272B2 (ja) * 2004-03-23 2010-10-20 株式会社東芝 半導体装置およびその製造方法
DE102004020834B4 (de) * 2004-04-28 2010-07-15 Qimonda Ag Herstellungsverfahren für eine Halbleiterstruktur
US7723238B2 (en) * 2004-06-16 2010-05-25 Tokyo Electron Limited Method for preventing striation at a sidewall of an opening of a resist during an etching process
US7101806B2 (en) * 2004-10-15 2006-09-05 International Business Machines Corporation Deep trench formation in semiconductor device fabrication
JP2006120832A (ja) * 2004-10-21 2006-05-11 Elpida Memory Inc 半導体装置及びその製造方法
US7109097B2 (en) * 2004-12-14 2006-09-19 Applied Materials, Inc. Process sequence for doped silicon fill of deep trenches
JP4673173B2 (ja) * 2005-09-15 2011-04-20 株式会社日立ハイテクノロジーズ プラズマエッチング方法
CN100517592C (zh) * 2006-04-30 2009-07-22 中芯国际集成电路制造(上海)有限公司 改进浅沟槽隔离间隙填充工艺的方法
US7709320B2 (en) * 2006-06-28 2010-05-04 International Business Machines Corporation Method of fabricating trench capacitors and memory cells using trench capacitors
US8129282B2 (en) * 2006-07-19 2012-03-06 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
JP4922718B2 (ja) * 2006-10-04 2012-04-25 株式会社日立ハイテクノロジーズ 絶縁膜ドライエッチング方法
US8614151B2 (en) * 2008-01-04 2013-12-24 Micron Technology, Inc. Method of etching a high aspect ratio contact
JP5102653B2 (ja) * 2008-02-29 2012-12-19 東京エレクトロン株式会社 プラズマエッチング方法、プラズマエッチング装置及びコンピュータ記憶媒体
US8120137B2 (en) * 2008-05-08 2012-02-21 Micron Technology, Inc. Isolation trench structure
US8277670B2 (en) * 2008-05-13 2012-10-02 Lam Research Corporation Plasma process with photoresist mask pretreatment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158306A (ja) * 2005-11-11 2007-06-21 Elpida Memory Inc 半導体集積回路装置の製造方法
WO2008038751A1 (en) * 2006-09-28 2008-04-03 Nikon Corporation Line width measuring method, image forming status detecting method, adjusting method, exposure method and device manufacturing method

Also Published As

Publication number Publication date
US20100297849A1 (en) 2010-11-25
TW201042719A (en) 2010-12-01
KR20100126149A (ko) 2010-12-01
JP2010272758A (ja) 2010-12-02

Similar Documents

Publication Publication Date Title
KR101167624B1 (ko) 피에칭재의 플라즈마 에칭방법
TWI637426B (zh) 單一平台多循環之間隔物沉積與蝕刻
TWI843802B (zh) 蝕刻半導體結構的方法和設備
US8987140B2 (en) Methods for etching through-silicon vias with tunable profile angles
JP5214596B2 (ja) プラズマ処理システムのマスクアンダーカットおよびノッチを最小化する方法
JP2008526025A (ja) 基板最適化のためのプラズマ処理ステップ交互実行方法及び装置
JP6277004B2 (ja) ドライエッチング方法
KR20170042727A (ko) 균일한 플라즈마 처리를 위한 노즐
US20190027372A1 (en) Etching method
CN100362632C (zh) 干蚀刻方法
US20130082030A1 (en) Plasma Tuning Rods in Microwave Resonator Plasma Sources
CN112119484A (zh) 等离子体处理方法
TW202401566A (zh) 電漿處理方法
CN109997212B (zh) 在有机层蚀刻中生成竖直轮廓的方法
US20250095964A1 (en) Method to control etch profile by rf pulsing
US20250299962A1 (en) Method for etching a layer through a patterned mask layer
TWI588939B (zh) A silicon through hole etching method
JP2639402B2 (ja) 酸化物層のテーパーエッチング方法
US20230094212A1 (en) Plasma etch process for fabricating high aspect ratio (har) features
TW202522551A (zh) 電漿處理裝置及其蝕刻方法
CN120199686A (zh) 处理半导体衬底的方法和设备
Wang et al. GaAs backside via-hole etching using ICP system
CN113053744A (zh) 半导体装置的制造方法
Pang Etching Technology
Vieira et al. Selective etching of polycrystalline silicon in a hexode type plasma etcher

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20150717

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20150717

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000