KR101006306B1 - 희생 스페이서를 사용하는 변형 채널 fet - Google Patents
희생 스페이서를 사용하는 변형 채널 fet Download PDFInfo
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- KR101006306B1 KR101006306B1 KR1020077006708A KR20077006708A KR101006306B1 KR 101006306 B1 KR101006306 B1 KR 101006306B1 KR 1020077006708 A KR1020077006708 A KR 1020077006708A KR 20077006708 A KR20077006708 A KR 20077006708A KR 101006306 B1 KR101006306 B1 KR 101006306B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
- H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
- H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
- H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/711,637 US7135724B2 (en) | 2004-09-29 | 2004-09-29 | Structure and method for making strained channel field effect transistor using sacrificial spacer |
| US10/711,637 | 2004-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070053300A KR20070053300A (ko) | 2007-05-23 |
| KR101006306B1 true KR101006306B1 (ko) | 2011-01-06 |
Family
ID=36098032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077006708A Expired - Fee Related KR101006306B1 (ko) | 2004-09-29 | 2005-09-29 | 희생 스페이서를 사용하는 변형 채널 fet |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7135724B2 (https=) |
| EP (1) | EP1805796B1 (https=) |
| JP (1) | JP5571286B2 (https=) |
| KR (1) | KR101006306B1 (https=) |
| CN (2) | CN101969030B (https=) |
| SG (1) | SG142307A1 (https=) |
| TW (1) | TWI370547B (https=) |
| WO (1) | WO2006039377A1 (https=) |
Families Citing this family (90)
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| JP3901696B2 (ja) * | 2004-02-19 | 2007-04-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP2005332993A (ja) * | 2004-05-20 | 2005-12-02 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
| EP1650796A3 (fr) * | 2004-10-20 | 2010-12-08 | STMicroelectronics (Crolles 2) SAS | Procédé de prise de contact sur une région d'un circuit intégré, en particulier sur les électrodes d'un transistor |
| US7217647B2 (en) * | 2004-11-04 | 2007-05-15 | International Business Machines Corporation | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern |
| US7397081B2 (en) * | 2004-12-13 | 2008-07-08 | International Business Machines Corporation | Sidewall semiconductor transistors |
| US20080121932A1 (en) | 2006-09-18 | 2008-05-29 | Pushkar Ranade | Active regions with compatible dielectric layers |
| US7545023B2 (en) * | 2005-03-22 | 2009-06-09 | United Microelectronics Corp. | Semiconductor transistor |
| US7446350B2 (en) * | 2005-05-10 | 2008-11-04 | International Business Machine Corporation | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer |
| US8003470B2 (en) | 2005-09-13 | 2011-08-23 | Infineon Technologies Ag | Strained semiconductor device and method of making the same |
| CN100536090C (zh) * | 2005-09-19 | 2009-09-02 | 中芯国际集成电路制造(上海)有限公司 | 形成cmos半导体器件的方法 |
| US20070132034A1 (en) * | 2005-12-14 | 2007-06-14 | Giuseppe Curello | Isolation body for semiconductor devices and method to form the same |
| US7696019B2 (en) * | 2006-03-09 | 2010-04-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
| DE102006015077B4 (de) * | 2006-03-31 | 2010-12-23 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit abgesenkten Drain- und Source-Gebieten und Verfahren zur Herstellung desselben |
| GB2449824B (en) * | 2006-03-31 | 2011-03-23 | Advanced Micro Devices Inc | Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions |
| DE102006019937B4 (de) * | 2006-04-28 | 2010-11-25 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines SOI-Transistors mit eingebetteter Verformungsschicht und einem reduzierten Effekt des potentialfreien Körpers |
| US20070257315A1 (en) * | 2006-05-04 | 2007-11-08 | International Business Machines Corporation | Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors |
| US7618866B2 (en) * | 2006-06-09 | 2009-11-17 | International Business Machines Corporation | Structure and method to form multilayer embedded stressors |
| DE102006030268B4 (de) * | 2006-06-30 | 2008-12-18 | Advanced Micro Devices Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, insbesondere eines FETs |
| EP1936696A1 (en) * | 2006-12-22 | 2008-06-25 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | A field effect transistor device and methods of production thereof |
| US7525161B2 (en) * | 2007-01-31 | 2009-04-28 | International Business Machines Corporation | Strained MOS devices using source/drain epitaxy |
| DE102007004862B4 (de) * | 2007-01-31 | 2014-01-30 | Globalfoundries Inc. | Verfahren zur Herstellung von Si-Ge enthaltenden Drain/Source-Gebieten in Transistoren mit geringerem Si/Ge-Verlust |
| US7544997B2 (en) | 2007-02-16 | 2009-06-09 | Freescale Semiconductor, Inc. | Multi-layer source/drain stressor |
| JP5003515B2 (ja) * | 2007-03-20 | 2012-08-15 | ソニー株式会社 | 半導体装置 |
| US7732285B2 (en) * | 2007-03-28 | 2010-06-08 | Intel Corporation | Semiconductor device having self-aligned epitaxial source and drain extensions |
| US7485519B2 (en) * | 2007-03-30 | 2009-02-03 | International Business Machines Corporation | After gate fabrication of field effect transistor having tensile and compressive regions |
| WO2008137724A1 (en) * | 2007-05-03 | 2008-11-13 | Dsm Solutions, Inc. | Strained channel p-type jfet and fabrication method thereof |
| US7615831B2 (en) * | 2007-10-26 | 2009-11-10 | International Business Machines Corporation | Structure and method for fabricating self-aligned metal contacts |
| KR100949804B1 (ko) * | 2007-12-14 | 2010-03-30 | 한국전자통신연구원 | 자기장 감지소자 |
| US7964923B2 (en) | 2008-01-07 | 2011-06-21 | International Business Machines Corporation | Structure and method of creating entirely self-aligned metallic contacts |
| US20100044804A1 (en) * | 2008-08-25 | 2010-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel high-k metal gate structure and method of making |
| DE102009015715B4 (de) * | 2009-03-31 | 2011-03-17 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung eines Transistorbauelements mit Bewahren der Integrität eines Gatestapel mit großem ε durch einen Versatzabstandshalter, der zum Bestimmen eines Abstands einer verformungsinduzierenden Halbleiterlegierung verwendet wird, und Transistorbauelement |
| US8198194B2 (en) * | 2010-03-23 | 2012-06-12 | Samsung Electronics Co., Ltd. | Methods of forming p-channel field effect transistors having SiGe source/drain regions |
| CN102315126A (zh) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | 半导体器件及其制作方法 |
| US8361859B2 (en) | 2010-11-09 | 2013-01-29 | International Business Machines Corporation | Stressed transistor with improved metastability |
| US9484432B2 (en) | 2010-12-21 | 2016-11-01 | Intel Corporation | Contact resistance reduction employing germanium overlayer pre-contact metalization |
| US8901537B2 (en) | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
| US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
| US8445363B2 (en) | 2011-04-21 | 2013-05-21 | United Microelectronics Corp. | Method of fabricating an epitaxial layer |
| US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
| US8426284B2 (en) | 2011-05-11 | 2013-04-23 | United Microelectronics Corp. | Manufacturing method for semiconductor structure |
| US8481391B2 (en) | 2011-05-18 | 2013-07-09 | United Microelectronics Corp. | Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure |
| US8431460B2 (en) | 2011-05-27 | 2013-04-30 | United Microelectronics Corp. | Method for fabricating semiconductor device |
| US8716750B2 (en) | 2011-07-25 | 2014-05-06 | United Microelectronics Corp. | Semiconductor device having epitaxial structures |
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| US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
| US8476169B2 (en) | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
| US8691659B2 (en) | 2011-10-26 | 2014-04-08 | United Microelectronics Corp. | Method for forming void-free dielectric layer |
| US8754448B2 (en) | 2011-11-01 | 2014-06-17 | United Microelectronics Corp. | Semiconductor device having epitaxial layer |
| US8647953B2 (en) | 2011-11-17 | 2014-02-11 | United Microelectronics Corp. | Method for fabricating first and second epitaxial cap layers |
| US8709930B2 (en) | 2011-11-25 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
| JP2013145800A (ja) * | 2012-01-13 | 2013-07-25 | National Institute Of Advanced Industrial & Technology | 半導体装置及びその製造方法 |
| JP5968708B2 (ja) * | 2012-01-23 | 2016-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US9680027B2 (en) * | 2012-03-07 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nickelide source/drain structures for CMOS transistors |
| CN103311184B (zh) * | 2012-03-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法,cmos的形成方法 |
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| CN102789106B (zh) * | 2012-04-24 | 2015-01-07 | 京东方科技集团股份有限公司 | 有机薄膜晶体管阵列基板及其制备方法以及显示装置 |
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| US8835243B2 (en) | 2012-05-04 | 2014-09-16 | United Microelectronics Corp. | Semiconductor process |
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| US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
| US8710632B2 (en) | 2012-09-07 | 2014-04-29 | United Microelectronics Corp. | Compound semiconductor epitaxial structure and method for fabricating the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101032018A (zh) | 2007-09-05 |
| US20060065914A1 (en) | 2006-03-30 |
| EP1805796B1 (en) | 2013-02-13 |
| EP1805796A4 (en) | 2008-10-01 |
| EP1805796A1 (en) | 2007-07-11 |
| CN101969030B (zh) | 2012-06-20 |
| WO2006039377A1 (en) | 2006-04-13 |
| JP5571286B2 (ja) | 2014-08-13 |
| US7135724B2 (en) | 2006-11-14 |
| CN101032018B (zh) | 2012-02-01 |
| KR20070053300A (ko) | 2007-05-23 |
| TWI370547B (en) | 2012-08-11 |
| TW200616225A (en) | 2006-05-16 |
| CN101969030A (zh) | 2011-02-09 |
| US7645656B2 (en) | 2010-01-12 |
| US20060292779A1 (en) | 2006-12-28 |
| SG142307A1 (en) | 2008-05-28 |
| JP2008515205A (ja) | 2008-05-08 |
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