KR100941106B1 - 전극 패턴 및 와이어본딩 방법 - Google Patents

전극 패턴 및 와이어본딩 방법 Download PDF

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Publication number
KR100941106B1
KR100941106B1 KR1020080020362A KR20080020362A KR100941106B1 KR 100941106 B1 KR100941106 B1 KR 100941106B1 KR 1020080020362 A KR1020080020362 A KR 1020080020362A KR 20080020362 A KR20080020362 A KR 20080020362A KR 100941106 B1 KR100941106 B1 KR 100941106B1
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South Korea
Prior art keywords
pattern
wire
electrode pattern
wire bond
wire bonding
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Expired - Fee Related
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KR1020080020362A
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English (en)
Korean (ko)
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KR20080085687A (ko
Inventor
요시히로 히사
츠토무 야마구치
히데유키 타나카
카즈노리 마츠오
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미쓰비시덴키 가부시키가이샤
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Publication of KR20080085687A publication Critical patent/KR20080085687A/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/01074Tungsten [W]
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    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
KR1020080020362A 2007-03-19 2008-03-05 전극 패턴 및 와이어본딩 방법 Expired - Fee Related KR100941106B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007070684 2007-03-19
JPJP-P-2007-00070684 2007-03-19
JP2008008066A JP5176557B2 (ja) 2007-03-19 2008-01-17 電極パターンおよびワイヤボンディング方法
JPJP-P-2008-00008066 2008-01-17

Publications (2)

Publication Number Publication Date
KR20080085687A KR20080085687A (ko) 2008-09-24
KR100941106B1 true KR100941106B1 (ko) 2010-02-10

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ID=39985396

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Application Number Title Priority Date Filing Date
KR1020080020362A Expired - Fee Related KR100941106B1 (ko) 2007-03-19 2008-03-05 전극 패턴 및 와이어본딩 방법

Country Status (4)

Country Link
JP (1) JP5176557B2 (enExample)
KR (1) KR100941106B1 (enExample)
CN (1) CN101272034B (enExample)
TW (1) TWI387171B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230097766A (ko) * 2021-12-24 2023-07-03 주식회사 유라코퍼레이션 Pcb기판

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5441590B2 (ja) * 2009-09-29 2014-03-12 大王製紙株式会社 パンツタイプ使い捨ておむつ
JP6901902B2 (ja) * 2017-04-27 2021-07-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN121097496A (zh) * 2025-11-10 2025-12-09 长春理工大学 一种提高半导体激光器调制速率的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291126A (ja) 1986-06-11 1987-12-17 Fuji Xerox Co Ltd パタ−ン認識マ−ク
JP2000012603A (ja) 1998-06-17 2000-01-14 Nec Corp 半導体装置
JP2001024303A (ja) 1999-07-09 2001-01-26 Nippon Avionics Co Ltd 認識マーク
US7042098B2 (en) 2003-07-07 2006-05-09 Freescale Semiconductor,Inc Bonding pad for a packaged integrated circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133638A (ja) * 1986-11-26 1988-06-06 Toshiba Corp ワイヤボンデイング方法
JP2621420B2 (ja) * 1988-09-28 1997-06-18 日本電気株式会社 半導体装置のボンディングパッド
JP2992427B2 (ja) * 1993-07-16 1999-12-20 株式会社カイジョー ワイヤボンディング装置及びその方法
JP3611948B2 (ja) * 1997-05-16 2005-01-19 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP4352579B2 (ja) * 2000-05-16 2009-10-28 沖電気工業株式会社 半導体チップ及びその製造方法
US6789724B2 (en) * 2001-07-06 2004-09-14 Erico International Corporation Welding apparatus and method
WO2003100850A1 (en) * 2002-05-28 2003-12-04 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them
JP2005183669A (ja) * 2003-12-19 2005-07-07 Tdk Corp 実装基板およびそれを用いた電子部品

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291126A (ja) 1986-06-11 1987-12-17 Fuji Xerox Co Ltd パタ−ン認識マ−ク
JP2000012603A (ja) 1998-06-17 2000-01-14 Nec Corp 半導体装置
JP2001024303A (ja) 1999-07-09 2001-01-26 Nippon Avionics Co Ltd 認識マーク
US7042098B2 (en) 2003-07-07 2006-05-09 Freescale Semiconductor,Inc Bonding pad for a packaged integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230097766A (ko) * 2021-12-24 2023-07-03 주식회사 유라코퍼레이션 Pcb기판
KR102706879B1 (ko) * 2021-12-24 2024-09-13 주식회사 유라코퍼레이션 Pcb기판

Also Published As

Publication number Publication date
TWI387171B (zh) 2013-02-21
CN101272034B (zh) 2010-09-29
TW200843265A (en) 2008-11-01
CN101272034A (zh) 2008-09-24
KR20080085687A (ko) 2008-09-24
JP5176557B2 (ja) 2013-04-03
JP2008263165A (ja) 2008-10-30

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