KR100902765B1 - 선입 선출 메모리 시스템 및 그 방법 - Google Patents

선입 선출 메모리 시스템 및 그 방법 Download PDF

Info

Publication number
KR100902765B1
KR100902765B1 KR1020037016664A KR20037016664A KR100902765B1 KR 100902765 B1 KR100902765 B1 KR 100902765B1 KR 1020037016664 A KR1020037016664 A KR 1020037016664A KR 20037016664 A KR20037016664 A KR 20037016664A KR 100902765 B1 KR100902765 B1 KR 100902765B1
Authority
KR
South Korea
Prior art keywords
fifo
multiplexer
data
input terminal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020037016664A
Other languages
English (en)
Korean (ko)
Other versions
KR20040010756A (ko
Inventor
김존제이.
콜린스리차드지.
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20040010756A publication Critical patent/KR20040010756A/ko
Application granted granted Critical
Publication of KR100902765B1 publication Critical patent/KR100902765B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Storing Facsimile Image Data (AREA)
KR1020037016664A 2001-06-20 2002-05-07 선입 선출 메모리 시스템 및 그 방법 Expired - Fee Related KR100902765B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/885,574 US6779055B2 (en) 2001-06-20 2001-06-20 First-in, first-out memory system having both simultaneous and alternating data access and method thereof
US09/885,574 2001-06-20
PCT/US2002/014555 WO2003001360A2 (en) 2001-06-20 2002-05-07 First-in, first-out memory system and method thereof

Publications (2)

Publication Number Publication Date
KR20040010756A KR20040010756A (ko) 2004-01-31
KR100902765B1 true KR100902765B1 (ko) 2009-06-15

Family

ID=25387224

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020037016664A Expired - Fee Related KR100902765B1 (ko) 2001-06-20 2002-05-07 선입 선출 메모리 시스템 및 그 방법

Country Status (9)

Country Link
US (1) US6779055B2 (enExample)
EP (1) EP1402340B1 (enExample)
JP (1) JP4076946B2 (enExample)
KR (1) KR100902765B1 (enExample)
CN (1) CN100377072C (enExample)
AU (1) AU2002305462A1 (enExample)
DE (1) DE60226141T2 (enExample)
TW (1) TWI229345B (enExample)
WO (1) WO2003001360A2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
EP1416373A3 (en) * 2002-10-31 2005-01-05 STMicroelectronics Pvt. Ltd Method and apparatus to reduce access time in synchronous fifos with zero latency overhead
KR101137064B1 (ko) 2004-01-07 2012-04-19 가부시키가이샤 니콘 적층 장치 및 집적 회로 소자의 적층 방법
MXPA06008043A (es) * 2004-01-16 2007-01-26 Trek 2000 Int Ltd Un dispositivo portatil de almacenamiento para grabar y reproducir datos.
CN101324863B (zh) * 2007-06-12 2012-07-04 中兴通讯股份有限公司 一种同步静态存储器的控制装置及方法
US8086936B2 (en) 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US8082482B2 (en) 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US20100269021A1 (en) * 2007-09-05 2010-10-21 Gower Kevin C Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
US7945745B2 (en) * 2007-09-17 2011-05-17 General Electric Company Methods and systems for exchanging data
KR20090059802A (ko) * 2007-12-07 2009-06-11 삼성전자주식회사 레지스터 업데이트 방법 및 이를 적용한 레지스터 및컴퓨터 시스템
US8140936B2 (en) 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US20100169570A1 (en) * 2008-12-31 2010-07-01 Michael Mesnier Providing differentiated I/O services within a hardware storage controller
KR20130102393A (ko) 2012-03-07 2013-09-17 삼성전자주식회사 Ｆｉｆｏ 메모리 장치 및 이를 포함하는 전자 장치
US9304693B1 (en) 2012-12-17 2016-04-05 Marvell International Ltd. System and method for writing data to a data storage structure
JP6049564B2 (ja) * 2013-07-29 2016-12-21 三菱電機株式会社 データトレース回路、集積回路およびデータトレース方法
US9824058B2 (en) * 2014-11-14 2017-11-21 Cavium, Inc. Bypass FIFO for multiple virtual channels
CN106603442B (zh) * 2016-12-14 2019-06-25 东北大学 一种片上网络的跨时钟域高速数据通信接口电路
US11061997B2 (en) * 2017-08-03 2021-07-13 Regents Of The University Of Minnesota Dynamic functional obfuscation
KR102697046B1 (ko) 2019-02-11 2024-08-20 삼성전자주식회사 비휘발성 메모리 장치
TWI771785B (zh) * 2020-10-29 2022-07-21 晶豪科技股份有限公司 資料先進先出(fifo)電路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807121A (en) 1984-06-21 1989-02-21 Cray Research, Inc. Peripheral interface system
EP0086943B1 (en) * 1982-02-18 1991-01-09 Rockwell International Corporation Adaptive spectrum shaping filter
US6233280B1 (en) 1997-12-31 2001-05-15 Lg Electronics Inc. Video decoder for high picture quality

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298954A (en) * 1979-04-30 1981-11-03 International Business Machines Corporation Alternating data buffers when one buffer is empty and another buffer is variably full of data
JPS59177782A (ja) 1983-03-25 1984-10-08 Nec Corp バツフアメモリ制御方式
FR2636448B1 (fr) 1988-09-15 1994-07-22 Finger Ulrich Dispositif d'acquisition de donnees pour processeur
NL8901661A (nl) * 1989-06-30 1991-01-16 Philips Nv Televisiesysteem voor digitale overdracht van beeldsignalen.
US5525985A (en) * 1990-12-28 1996-06-11 Eaton Corporation Sure chip
US5305319A (en) 1991-01-31 1994-04-19 Chips And Technologies, Inc. FIFO for coupling asynchronous channels
DE4226952A1 (de) * 1992-08-14 1994-02-17 Deutsche Forsch Luft Raumfahrt Rahmen-Synchronisierer für Telemetrie-Systeme
KR0126330Y1 (ko) * 1993-10-23 1998-12-15 김광호 텔레비젼 수상기의 더블스캔 제어회로
JPH10283088A (ja) 1997-04-02 1998-10-23 Oki Electric Ind Co Ltd シリアル通信回路
KR19980077474A (ko) * 1997-04-19 1998-11-16 김영환 비디오 신호의 스캔방식 변환장치 및 그 제어방법
US6055616A (en) 1997-06-25 2000-04-25 Sun Microsystems, Inc. System for efficient implementation of multi-ported logic FIFO structures in a processor
US6073190A (en) * 1997-07-18 2000-06-06 Micron Electronics, Inc. System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0086943B1 (en) * 1982-02-18 1991-01-09 Rockwell International Corporation Adaptive spectrum shaping filter
US4807121A (en) 1984-06-21 1989-02-21 Cray Research, Inc. Peripheral interface system
US6233280B1 (en) 1997-12-31 2001-05-15 Lg Electronics Inc. Video decoder for high picture quality

Also Published As

Publication number Publication date
US6779055B2 (en) 2004-08-17
EP1402340A2 (en) 2004-03-31
CN100377072C (zh) 2008-03-26
TWI229345B (en) 2005-03-11
WO2003001360A3 (en) 2003-10-16
AU2002305462A1 (en) 2003-01-08
WO2003001360A2 (en) 2003-01-03
DE60226141T2 (de) 2009-05-20
JP2005505029A (ja) 2005-02-17
US20020199042A1 (en) 2002-12-26
CN1524215A (zh) 2004-08-25
JP4076946B2 (ja) 2008-04-16
EP1402340B1 (en) 2008-04-16
DE60226141D1 (de) 2008-05-29
KR20040010756A (ko) 2004-01-31

Similar Documents

Publication Publication Date Title
KR100902765B1 (ko) 선입 선출 메모리 시스템 및 그 방법
KR0123239B1 (ko) 선입선출방식(fifo) 메모리
US5490257A (en) RAM based FIFO memory half-full detection apparatus and method
US6802036B2 (en) High-speed first-in-first-out buffer
WO2001042926A1 (en) Interface for a memory unit
CN117280298A (zh) 一种寄存器阵列电路和访问寄存器阵列的方法
US7136309B2 (en) FIFO with multiple data inputs and method thereof
US7257687B2 (en) Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system
JPH11219344A (ja) プロセッサ間ネットワークのフロー制御方法および装置
US7035908B1 (en) Method for multiprocessor communication within a shared memory architecture
US6510483B1 (en) Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports
EP1714210B1 (en) A fifo memory device with non-volatile storage stage
EP0020972B1 (en) Program controlled microprocessing apparatus
US6486704B1 (en) Programmable burst FIFO
KR100429865B1 (ko) 필 상태검사 회로 및 이를 이용한 fifo메모리
EP1459291B1 (en) Digital line delay using a single port memory
KR100475093B1 (ko) 둘 이상의 입력포트를 구비하는 집적 회로 장치 및 시스템
JPH05265701A (ja) Ｆｉｆｏメモリ
JPS633392B2 (enExample)
KR100208794B1 (ko) 레지스터 공유회로
JP2005174090A (ja) データ転送回路
JP2595707B2 (ja) メモリ装置
KR100224725B1 (ko) 선입선출기
JPH04105298A (ja) 半導体メモリ集積回路
JPS62209640A (ja) 記憶装置

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

PE0801 Dismissal of amendment

St.27 status event code: A-2-2-P10-P12-nap-PE0801

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20130524

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20140527

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20150609

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20150609

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301