AU2002305462A1 - First-in, first-out memory system and method thereof - Google Patents

First-in, first-out memory system and method thereof

Info

Publication number
AU2002305462A1
AU2002305462A1 AU2002305462A AU2002305462A AU2002305462A1 AU 2002305462 A1 AU2002305462 A1 AU 2002305462A1 AU 2002305462 A AU2002305462 A AU 2002305462A AU 2002305462 A AU2002305462 A AU 2002305462A AU 2002305462 A1 AU2002305462 A1 AU 2002305462A1
Authority
AU
Australia
Prior art keywords
memory system
out memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002305462A
Other languages
English (en)
Inventor
Richard G. Collins
John J. Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2002305462A1 publication Critical patent/AU2002305462A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Storing Facsimile Image Data (AREA)
AU2002305462A 2001-06-20 2002-05-07 First-in, first-out memory system and method thereof Abandoned AU2002305462A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/885,574 US6779055B2 (en) 2001-06-20 2001-06-20 First-in, first-out memory system having both simultaneous and alternating data access and method thereof
US09/885,574 2001-06-20
PCT/US2002/014555 WO2003001360A2 (en) 2001-06-20 2002-05-07 First-in, first-out memory system and method thereof

Publications (1)

Publication Number Publication Date
AU2002305462A1 true AU2002305462A1 (en) 2003-01-08

Family

ID=25387224

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002305462A Abandoned AU2002305462A1 (en) 2001-06-20 2002-05-07 First-in, first-out memory system and method thereof

Country Status (9)

Country Link
US (1) US6779055B2 (enExample)
EP (1) EP1402340B1 (enExample)
JP (1) JP4076946B2 (enExample)
KR (1) KR100902765B1 (enExample)
CN (1) CN100377072C (enExample)
AU (1) AU2002305462A1 (enExample)
DE (1) DE60226141T2 (enExample)
TW (1) TWI229345B (enExample)
WO (1) WO2003001360A2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
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US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
EP1416373A3 (en) * 2002-10-31 2005-01-05 STMicroelectronics Pvt. Ltd Method and apparatus to reduce access time in synchronous fifos with zero latency overhead
WO2005067046A1 (ja) 2004-01-07 2005-07-21 Nikon Corporation 積層装置及び集積回路素子の積層方法
GB2429866B (en) * 2004-01-16 2009-05-06 Trek 2000 Int Ltd A portable storage device for recording and playing back data
CN101324863B (zh) * 2007-06-12 2012-07-04 中兴通讯股份有限公司 一种同步静态存储器的控制装置及方法
US8086936B2 (en) 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US8082482B2 (en) 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US20100269021A1 (en) * 2007-09-05 2010-10-21 Gower Kevin C Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
US7945745B2 (en) * 2007-09-17 2011-05-17 General Electric Company Methods and systems for exchanging data
KR20090059802A (ko) * 2007-12-07 2009-06-11 삼성전자주식회사 레지스터 업데이트 방법 및 이를 적용한 레지스터 및컴퓨터 시스템
US8140936B2 (en) 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US20100169570A1 (en) * 2008-12-31 2010-07-01 Michael Mesnier Providing differentiated I/O services within a hardware storage controller
KR20130102393A (ko) 2012-03-07 2013-09-17 삼성전자주식회사 Ｆｉｆｏ 메모리 장치 및 이를 포함하는 전자 장치
US9304693B1 (en) 2012-12-17 2016-04-05 Marvell International Ltd. System and method for writing data to a data storage structure
JP6049564B2 (ja) * 2013-07-29 2016-12-21 三菱電機株式会社 データトレース回路、集積回路およびデータトレース方法
US9824058B2 (en) * 2014-11-14 2017-11-21 Cavium, Inc. Bypass FIFO for multiple virtual channels
CN106603442B (zh) * 2016-12-14 2019-06-25 东北大学 一种片上网络的跨时钟域高速数据通信接口电路
US11061997B2 (en) * 2017-08-03 2021-07-13 Regents Of The University Of Minnesota Dynamic functional obfuscation
KR102697046B1 (ko) 2019-02-11 2024-08-20 삼성전자주식회사 비휘발성 메모리 장치
TWI771785B (zh) * 2020-10-29 2022-07-21 晶豪科技股份有限公司 資料先進先出(fifo)電路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298954A (en) * 1979-04-30 1981-11-03 International Business Machines Corporation Alternating data buffers when one buffer is empty and another buffer is variably full of data
US4524424A (en) * 1982-02-18 1985-06-18 Rockwell International Corporation Adaptive spectrum shaping filter
JPS59177782A (ja) 1983-03-25 1984-10-08 Nec Corp バツフアメモリ制御方式
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
FR2636448B1 (fr) 1988-09-15 1994-07-22 Finger Ulrich Dispositif d'acquisition de donnees pour processeur
NL8901661A (nl) * 1989-06-30 1991-01-16 Philips Nv Televisiesysteem voor digitale overdracht van beeldsignalen.
US5525985A (en) * 1990-12-28 1996-06-11 Eaton Corporation Sure chip
US5305319A (en) 1991-01-31 1994-04-19 Chips And Technologies, Inc. FIFO for coupling asynchronous channels
DE4226952A1 (de) * 1992-08-14 1994-02-17 Deutsche Forsch Luft Raumfahrt Rahmen-Synchronisierer für Telemetrie-Systeme
KR0126330Y1 (ko) * 1993-10-23 1998-12-15 김광호 텔레비젼 수상기의 더블스캔 제어회로
JPH10283088A (ja) 1997-04-02 1998-10-23 Oki Electric Ind Co Ltd シリアル通信回路
KR19980077474A (ko) * 1997-04-19 1998-11-16 김영환 비디오 신호의 스캔방식 변환장치 및 그 제어방법
US6055616A (en) 1997-06-25 2000-04-25 Sun Microsystems, Inc. System for efficient implementation of multi-ported logic FIFO structures in a processor
US6073190A (en) * 1997-07-18 2000-06-06 Micron Electronics, Inc. System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
KR100249235B1 (ko) * 1997-12-31 2000-03-15 구자홍 에이치디티브이 비디오 디코더

Also Published As

Publication number Publication date
US6779055B2 (en) 2004-08-17
CN100377072C (zh) 2008-03-26
US20020199042A1 (en) 2002-12-26
EP1402340B1 (en) 2008-04-16
TWI229345B (en) 2005-03-11
DE60226141T2 (de) 2009-05-20
JP2005505029A (ja) 2005-02-17
KR20040010756A (ko) 2004-01-31
JP4076946B2 (ja) 2008-04-16
DE60226141D1 (de) 2008-05-29
WO2003001360A2 (en) 2003-01-03
WO2003001360A3 (en) 2003-10-16
EP1402340A2 (en) 2004-03-31
CN1524215A (zh) 2004-08-25
KR100902765B1 (ko) 2009-06-15

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase