KR100847926B1 - 다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동 - Google Patents

다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동 Download PDF

Info

Publication number
KR100847926B1
KR100847926B1 KR1020037017288A KR20037017288A KR100847926B1 KR 100847926 B1 KR100847926 B1 KR 100847926B1 KR 1020037017288 A KR1020037017288 A KR 1020037017288A KR 20037017288 A KR20037017288 A KR 20037017288A KR 100847926 B1 KR100847926 B1 KR 100847926B1
Authority
KR
South Korea
Prior art keywords
atomic
dielectric layer
delete delete
sealing
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020037017288A
Other languages
English (en)
Korean (ko)
Other versions
KR20040032119A (ko
Inventor
메이넨헤르만
와이드너윌리암케네스
이아코피프란체스카
말휴트레스테판
Original Assignee
다우 코닝 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다우 코닝 코포레이션 filed Critical 다우 코닝 코포레이션
Publication of KR20040032119A publication Critical patent/KR20040032119A/ko
Application granted granted Critical
Publication of KR100847926B1 publication Critical patent/KR100847926B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Laminated Bodies (AREA)
KR1020037017288A 2001-07-02 2002-06-25 다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동 Expired - Fee Related KR100847926B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US30246901P 2001-07-02 2001-07-02
US60/302,469 2001-07-02
PCT/US2002/020704 WO2003005438A2 (en) 2001-07-02 2002-06-25 Improved metal barrier behavior by sic:h deposition on porous materials

Publications (2)

Publication Number Publication Date
KR20040032119A KR20040032119A (ko) 2004-04-14
KR100847926B1 true KR100847926B1 (ko) 2008-07-22

Family

ID=23167846

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020037017288A Expired - Fee Related KR100847926B1 (ko) 2001-07-02 2002-06-25 다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동

Country Status (5)

Country Link
US (1) US6541842B2 (enExample)
JP (1) JP2004535065A (enExample)
KR (1) KR100847926B1 (enExample)
CN (1) CN1596466A (enExample)
WO (1) WO2003005438A2 (enExample)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475276B1 (en) 1999-10-15 2002-11-05 Asm Microchemistry Oy Production of elemental thin films using a boron-containing reducing agent
US6759325B2 (en) * 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US7597715B2 (en) 2005-04-21 2009-10-06 Biomet Manufacturing Corp. Method and apparatus for use of porous implants
US8123814B2 (en) 2001-02-23 2012-02-28 Biomet Manufacturing Corp. Method and appartus for acetabular reconstruction
EP1425435A2 (en) * 2001-09-14 2004-06-09 Asm International N.V. Metal nitride deposition by ald using gettering reactant
US6759327B2 (en) * 2001-10-09 2004-07-06 Applied Materials Inc. Method of depositing low k barrier layers
US6838393B2 (en) * 2001-12-14 2005-01-04 Applied Materials, Inc. Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide
US7091137B2 (en) * 2001-12-14 2006-08-15 Applied Materials Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US6541397B1 (en) * 2002-03-29 2003-04-01 Applied Materials, Inc. Removable amorphous carbon CMP stop
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7749563B2 (en) * 2002-10-07 2010-07-06 Applied Materials, Inc. Two-layer film for next generation damascene barrier application with good oxidation resistance
JP2004200203A (ja) * 2002-12-16 2004-07-15 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
CN100407400C (zh) * 2003-05-29 2008-07-30 日本电气株式会社 布线结构
TWI257120B (en) * 2003-06-18 2006-06-21 Fujitsu Ltd Method for manufacturing semiconductor device
KR100964194B1 (ko) * 2003-07-18 2010-06-17 매그나칩 반도체 유한회사 반도체 소자의 절연막 형성 방법
US7052990B2 (en) * 2003-09-03 2006-05-30 Infineon Technologies Ag Sealed pores in low-k material damascene conductive structures
US7553769B2 (en) * 2003-10-10 2009-06-30 Tokyo Electron Limited Method for treating a dielectric film
US7157373B2 (en) 2003-12-11 2007-01-02 Infineon Technologies Ag Sidewall sealing of porous dielectric materials
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
US7638440B2 (en) * 2004-03-12 2009-12-29 Applied Materials, Inc. Method of depositing an amorphous carbon film for etch hardmask application
US7407893B2 (en) * 2004-03-05 2008-08-05 Applied Materials, Inc. Liquid precursors for the CVD deposition of amorphous carbon films
US7030041B2 (en) * 2004-03-15 2006-04-18 Applied Materials Inc. Adhesion improvement for low k dielectrics
US7229911B2 (en) * 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US20050233555A1 (en) * 2004-04-19 2005-10-20 Nagarajan Rajagopalan Adhesion improvement for low k dielectrics to conductive materials
US7244674B2 (en) * 2004-04-27 2007-07-17 Agency For Science Technology And Research Process of forming a composite diffusion barrier in copper/organic low-k damascene technology
US7015150B2 (en) * 2004-05-26 2006-03-21 International Business Machines Corporation Exposed pore sealing post patterning
US20050277302A1 (en) * 2004-05-28 2005-12-15 Nguyen Son V Advanced low dielectric constant barrier layers
US7229041B2 (en) * 2004-06-30 2007-06-12 Ohio Central Steel Company Lifting lid crusher
US7288205B2 (en) * 2004-07-09 2007-10-30 Applied Materials, Inc. Hermetic low dielectric constant layer for barrier applications
JP4903373B2 (ja) * 2004-09-02 2012-03-28 ローム株式会社 半導体装置の製造方法
JP4903374B2 (ja) * 2004-09-02 2012-03-28 ローム株式会社 半導体装置の製造方法
JP4798334B2 (ja) * 2004-10-15 2011-10-19 Ｊｓｒ株式会社 表面疎水化用組成物、表面疎水化方法、半導体装置およびその製造方法
US20060099802A1 (en) * 2004-11-10 2006-05-11 Jing-Cheng Lin Diffusion barrier for damascene structures
US7678682B2 (en) * 2004-11-12 2010-03-16 Axcelis Technologies, Inc. Ultraviolet assisted pore sealing of porous low k dielectric films
US20060113675A1 (en) * 2004-12-01 2006-06-01 Chung-Liang Chang Barrier material and process for Cu interconnect
US7229909B2 (en) * 2004-12-09 2007-06-12 International Business Machines Corporation Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes
US20060131700A1 (en) * 2004-12-22 2006-06-22 David Moses M Flexible electronic circuit articles and methods of making thereof
JP4408816B2 (ja) * 2005-01-07 2010-02-03 富士通株式会社 半導体装置の製造方法
JP5324734B2 (ja) * 2005-01-21 2013-10-23 インターナショナル・ビジネス・マシーンズ・コーポレーション 誘電体材料とその製造方法
US7135402B2 (en) * 2005-02-01 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing pores of low-k dielectrics using CxHy
US7365026B2 (en) * 2005-02-01 2008-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. CxHy sacrificial layer for cu/low-k interconnects
JP4201002B2 (ja) * 2005-03-28 2008-12-24 セイコーエプソン株式会社 液晶装置、その製造方法およびプロジェクタ
US8021432B2 (en) 2005-12-05 2011-09-20 Biomet Manufacturing Corp. Apparatus for use of porous implants
US8266780B2 (en) * 2005-04-21 2012-09-18 Biomet Manufacturing Corp. Method and apparatus for use of porous implants
US8292967B2 (en) * 2005-04-21 2012-10-23 Biomet Manufacturing Corp. Method and apparatus for use of porous implants
US8066778B2 (en) * 2005-04-21 2011-11-29 Biomet Manufacturing Corp. Porous metal cup with cobalt bearing surface
US7335586B2 (en) * 2005-06-10 2008-02-26 Intel Corporation Sealing porous dielectric material using plasma-induced surface polymerization
US7915735B2 (en) * 2005-08-05 2011-03-29 Micron Technology, Inc. Selective metal deposition over dielectric layers
JP4965830B2 (ja) 2005-08-12 2012-07-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4747755B2 (ja) * 2005-09-20 2011-08-17 独立行政法人産業技術総合研究所 有機絶縁膜とその作製方法，及び有機絶縁膜を用いた半導体装置
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7635447B2 (en) * 2006-02-17 2009-12-22 Biomet Manufacturing Corp. Method and apparatus for forming porous metal implants
US7564136B2 (en) * 2006-02-24 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration scheme for Cu/low-k interconnects
JP5372323B2 (ja) * 2006-03-29 2013-12-18 富士通株式会社 界面ラフネス緩和膜、これを用いた配線層および半導体装置ならびに半導体装置の製造方法
US20070286954A1 (en) * 2006-06-13 2007-12-13 Applied Materials, Inc. Methods for low temperature deposition of an amorphous carbon layer
DE102006056626B4 (de) * 2006-11-30 2024-12-19 Advanced Micro Devices, Inc. Verfahren zum Bilden einer Öffnung in einer Metallisierungsstruktur einer Halbleitervorrichtung mittels eines selbstbeschränkenden Abscheideprozesses
WO2009042150A1 (en) * 2007-09-25 2009-04-02 Biomet Manufacturing Corp. Cementless tibial tray
US20090093128A1 (en) * 2007-10-08 2009-04-09 Martin Jay Seamons Methods for high temperature deposition of an amorphous carbon layer
KR20090048178A (ko) * 2007-11-09 2009-05-13 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US20090269923A1 (en) * 2008-04-25 2009-10-29 Lee Sang M Adhesion and electromigration improvement between dielectric and conductive layers
KR20100134733A (ko) 2008-06-17 2010-12-23 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
JP5332442B2 (ja) * 2008-09-19 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
CN103467506B (zh) * 2008-10-20 2016-03-23 陶氏康宁公司 Cvd前体
US9653327B2 (en) 2011-05-12 2017-05-16 Applied Materials, Inc. Methods of removing a material layer from a substrate using water vapor treatment
CN103943789A (zh) * 2014-04-18 2014-07-23 深圳市华星光电技术有限公司 Oled器件及其制备方法
US9230900B1 (en) * 2014-12-18 2016-01-05 Intel Corporation Ground via clustering for crosstalk mitigation
US9515017B2 (en) 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
JP6499001B2 (ja) * 2015-04-20 2019-04-10 東京エレクトロン株式会社 多孔質膜をエッチングする方法
FR3042067A1 (fr) 2015-10-01 2017-04-07 Stmicroelectronics Rousset Protection contre le claquage premature de dielectriques poreux interlignes au sein d'un circuit integre
US9997451B2 (en) 2016-06-30 2018-06-12 International Business Machines Corporation Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
US10763419B2 (en) * 2017-06-02 2020-09-01 Northrop Grumman Systems Corporation Deposition methodology for superconductor interconnects
JP6910387B2 (ja) * 2019-03-05 2021-07-28 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
US11315893B2 (en) * 2020-03-25 2022-04-26 Nanya Technology Corporation Semiconductor device with composite connection structure and method for fabricating the same
TW202200828A (zh) 2020-06-24 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 含鉬薄膜的氣相沉積

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171945B1 (en) 1998-10-22 2001-01-09 Applied Materials, Inc. CVD nanoporous silica low dielectric constant films

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2546696B2 (ja) * 1987-12-17 1996-10-23 富士通株式会社 シリコン炭化層構造
US5818071A (en) * 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
US6156651A (en) * 1996-12-13 2000-12-05 Texas Instruments Incorporated Metallization method for porous dielectrics
TW405223B (en) * 1998-07-28 2000-09-11 United Microelectronics Corp Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole
US6231989B1 (en) * 1998-11-20 2001-05-15 Dow Corning Corporation Method of forming coatings
US6180518B1 (en) * 1999-10-29 2001-01-30 Lucent Technologies Inc. Method for forming vias in a low dielectric constant material
JP3365554B2 (ja) * 2000-02-07 2003-01-14 キヤノン販売株式会社 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171945B1 (en) 1998-10-22 2001-01-09 Applied Materials, Inc. CVD nanoporous silica low dielectric constant films

Also Published As

Publication number Publication date
US6541842B2 (en) 2003-04-01
CN1596466A (zh) 2005-03-16
JP2004535065A (ja) 2004-11-18
US20030001282A1 (en) 2003-01-02
KR20040032119A (ko) 2004-04-14
WO2003005438A2 (en) 2003-01-16
WO2003005438A3 (en) 2003-05-01

Similar Documents

Publication Publication Date Title
KR100847926B1 (ko) 다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동
US7122481B2 (en) Sealing porous dielectrics with silane coupling reagents
KR100960755B1 (ko) 다마신 분야에서 유전체 재료를 증착하는 방법
US7851384B2 (en) Method to mitigate impact of UV and E-beam exposure on semiconductor device film properties by use of a bilayer film
US8927442B1 (en) SiCOH hardmask with graded transition layers
US7091137B2 (en) Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US7088003B2 (en) Structures and methods for integration of ultralow-k dielectrics with improved reliability
US7015150B2 (en) Exposed pore sealing post patterning
US7646077B2 (en) Methods and structure for forming copper barrier layers integral with semiconductor substrates structures
US7439174B2 (en) Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
US7193325B2 (en) Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
US20040214446A1 (en) Nitrogen-free dielectric anti-reflective coating and hardmask
JP5174435B2 (ja) ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法
US20090014880A1 (en) Dual damascene process flow enabling minimal ulk film modification and enhanced stack integrity
US8921235B2 (en) Controlled air gap formation
KR100479796B1 (ko) 반도체 소자 및 이의 제조 방법
US7105460B2 (en) Nitrogen-free dielectric anti-reflective coating and hardmask
US20040061236A1 (en) Semiconductor device provided with a dielectric film including porous structure and manufacturing method thereof
US8981563B2 (en) Semiconductor device and method of manufacturing the same
KR20050084286A (ko) 나이트로겐-비함유 유전성 비반사 코팅부 및 하드마스크
JP2009094123A (ja) 半導体装置の製造方法
US7678687B2 (en) Method for manufacturing semiconductor device and semiconductor device

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20130620

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20140702

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20150618

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20160717

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20160717

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18 Changes to party contact information recorded

Free format text: ST27 STATUS EVENT CODE: A-5-5-R10-R18-OTH-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000