KR100732022B1 - 다층 리드 프레임 및 이를 사용한 반도체 장치 - Google Patents
다층 리드 프레임 및 이를 사용한 반도체 장치 Download PDFInfo
- Publication number
- KR100732022B1 KR100732022B1 KR1020010021721A KR20010021721A KR100732022B1 KR 100732022 B1 KR100732022 B1 KR 100732022B1 KR 1020010021721 A KR1020010021721 A KR 1020010021721A KR 20010021721 A KR20010021721 A KR 20010021721A KR 100732022 B1 KR100732022 B1 KR 100732022B1
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- KR
- South Korea
- Prior art keywords
- lead frame
- semiconductor device
- heat spreader
- semiconductor element
- lead
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (3)
- 히트 스프레더와 내측 리드를 적층하여 이루어진 다층 리드 프레임에 있어서,상기 내측 리드의 선단으로 향하는 중도부에, 상기 히트 스프레더의 반도체 소자 탑재면에 대하여 상하방향으로 굴곡된 절곡부를 설치하고, 상기 내측 리드의 선단부를 상기 히트 스프레더의 반도체 소자 탑재면의 테두리 부분에 접착시킨 것을 특징으로 하는 다층 리드 프레임.
- 청구항 1에 기재된 상기 다층 리드 프레임에 반도체 소자가 탑재되고,상기 반도체 소자와 상기 내측 리드가 전기적으로 접속되는 동시에,상기 히트 스프레더의 상기 반도체 소자 탑재면의 반대면이 노출되도록 상기 내측 리드, 상기 반도체 소자, 및 상기 히트 스프레더의 각각이 수지 밀봉된 것을 특징으로 하는 반도체 장치.
- 제 2 항에 있어서,상기 반도체 소자의 탑재면 테두리 부분에 상기 내측 리드의 표면 일부가 노출되어 상기 노출된 표면이 상기 반도체 소자의 외부 접속 단자로 되고, 상기 반도체 소자의 외주로부터 상기 다층 리드 프레임의 외측 리드가 돌출되지 않는 것을 특징으로 하는 반도체 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-156165 | 2000-05-26 | ||
JP2000156165A JP2001339029A (ja) | 2000-05-26 | 2000-05-26 | 多層リードフレーム及びこれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010107549A KR20010107549A (ko) | 2001-12-07 |
KR100732022B1 true KR100732022B1 (ko) | 2007-06-27 |
Family
ID=18660992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010021721A KR100732022B1 (ko) | 2000-05-26 | 2001-04-23 | 다층 리드 프레임 및 이를 사용한 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2001339029A (ko) |
KR (1) | KR100732022B1 (ko) |
TW (1) | TW483139B (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100621555B1 (ko) * | 2004-02-04 | 2006-09-14 | 삼성전자주식회사 | 리드 프레임, 이를 이용한 반도체 칩 패키지 및 그의 제조방법 |
JP6211956B2 (ja) * | 2014-03-10 | 2017-10-11 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
CN117157755A (zh) * | 2021-04-01 | 2023-12-01 | 罗姆股份有限公司 | 半导体器件和半导体器件的制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970053631A (ko) * | 1995-12-15 | 1997-07-31 | 문정환 | 반도체 다핀 패키지 및 그 제조방법 |
KR970077540A (ko) * | 1996-05-17 | 1997-12-12 | 문정환 | 칩 사이즈 패키지의 제조방법 |
KR19980014930A (ko) * | 1996-08-17 | 1998-05-25 | 김광호 | 이층다이패드 구조를 갖는 리드 프레임을 이용한 트랜지스터 패키지 |
KR19980027862A (ko) * | 1996-10-18 | 1998-07-15 | 김광호 | 더미 접착부를 갖는 리드 온 칩(lead on chip;LOC)용 리드 프레임 및 그를 이용한 반도체 칩 패키지 |
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2000
- 2000-05-26 JP JP2000156165A patent/JP2001339029A/ja active Pending
-
2001
- 2001-04-18 TW TW090109266A patent/TW483139B/zh not_active IP Right Cessation
- 2001-04-23 KR KR1020010021721A patent/KR100732022B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970053631A (ko) * | 1995-12-15 | 1997-07-31 | 문정환 | 반도체 다핀 패키지 및 그 제조방법 |
KR970077540A (ko) * | 1996-05-17 | 1997-12-12 | 문정환 | 칩 사이즈 패키지의 제조방법 |
KR19980014930A (ko) * | 1996-08-17 | 1998-05-25 | 김광호 | 이층다이패드 구조를 갖는 리드 프레임을 이용한 트랜지스터 패키지 |
KR19980027862A (ko) * | 1996-10-18 | 1998-07-15 | 김광호 | 더미 접착부를 갖는 리드 온 칩(lead on chip;LOC)용 리드 프레임 및 그를 이용한 반도체 칩 패키지 |
Also Published As
Publication number | Publication date |
---|---|
KR20010107549A (ko) | 2001-12-07 |
JP2001339029A (ja) | 2001-12-07 |
TW483139B (en) | 2002-04-11 |
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