KR100721358B1 - 강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법 - Google Patents

강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법 Download PDF

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Publication number
KR100721358B1
KR100721358B1 KR1020060003577A KR20060003577A KR100721358B1 KR 100721358 B1 KR100721358 B1 KR 100721358B1 KR 1020060003577 A KR1020060003577 A KR 1020060003577A KR 20060003577 A KR20060003577 A KR 20060003577A KR 100721358 B1 KR100721358 B1 KR 100721358B1
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South Korea
Prior art keywords
film
forming
interlayer insulating
layer
insulating film
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KR1020060003577A
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English (en)
Korean (ko)
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KR20070025902A (ko
Inventor
나오야 사시다
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후지쯔 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
KR1020060003577A 2005-09-01 2006-01-12 강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법 KR100721358B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005253909A JP4617227B2 (ja) 2005-09-01 2005-09-01 強誘電体メモリ装置およびその製造方法
JPJP-P-2005-00253909 2005-09-01

Publications (2)

Publication Number Publication Date
KR20070025902A KR20070025902A (ko) 2007-03-08
KR100721358B1 true KR100721358B1 (ko) 2007-05-25

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KR1020060003577A KR100721358B1 (ko) 2005-09-01 2006-01-12 강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법

Country Status (4)

Country Link
US (3) US7579641B2 (zh)
JP (1) JP4617227B2 (zh)
KR (1) KR100721358B1 (zh)
CN (1) CN100511684C (zh)

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JP4702550B2 (ja) * 2006-01-27 2011-06-15 セイコーエプソン株式会社 半導体装置の製造方法
JP4802777B2 (ja) * 2006-03-13 2011-10-26 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4797717B2 (ja) * 2006-03-14 2011-10-19 セイコーエプソン株式会社 強誘電体メモリ装置、強誘電体メモリ装置の製造方法
JP4683224B2 (ja) * 2006-03-15 2011-05-18 セイコーエプソン株式会社 強誘電体メモリの製造方法
JP5140935B2 (ja) * 2006-03-28 2013-02-13 富士通セミコンダクター株式会社 マグネトロンスパッタ成膜装置、及び半導体装置の製造方法
US8247855B2 (en) * 2006-09-12 2012-08-21 Texas Instruments Incorporated Enhanced local interconnects employing ferroelectric electrodes
JP2008235815A (ja) * 2007-03-23 2008-10-02 Toshiba Corp 不揮発性記憶装置
JP4479770B2 (ja) 2007-09-14 2010-06-09 セイコーエプソン株式会社 強誘電体メモリの製造方法
JP5440493B2 (ja) 2008-03-31 2014-03-12 富士通セミコンダクター株式会社 強誘電体メモリとその製造方法、及び強誘電体キャパシタの製造方法
US20100245617A1 (en) * 2009-03-31 2010-09-30 Gary Stephen Shuster Automated white balancing in digital photography
JP2010278074A (ja) * 2009-05-26 2010-12-09 Fujitsu Semiconductor Ltd 電子装置およびその製造方法
US8395196B2 (en) 2010-11-16 2013-03-12 International Business Machines Corporation Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip
JP5690207B2 (ja) * 2011-05-11 2015-03-25 ルネサスエレクトロニクス株式会社 半導体装置
US9184260B2 (en) * 2013-11-14 2015-11-10 GlobalFoundries, Inc. Methods for fabricating integrated circuits with robust gate electrode structure protection
US10090360B2 (en) 2015-02-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor structure including a plurality of trenches
US20170092753A1 (en) * 2015-09-29 2017-03-30 Infineon Technologies Austria Ag Water and Ion Barrier for III-V Semiconductor Devices
US10062630B2 (en) 2015-12-31 2018-08-28 Infineon Technologies Austria Ag Water and ion barrier for the periphery of III-V semiconductor dies
CN112582398A (zh) * 2019-09-30 2021-03-30 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US20210408117A1 (en) * 2020-06-29 2021-12-30 Taiwan Semiconductor Manufacturing Company Limited Multi-gate selector switches for memory cells and methods of forming the same

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JP2002280523A (ja) * 2001-03-16 2002-09-27 Nec Corp 半導体記憶装置とその製造方法
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KR100964834B1 (ko) * 2005-09-01 2010-06-24 후지쯔 세미컨덕터 가부시키가이샤 강유전체 메모리 장치 및 그 제조 방법, 반도체장치의 제조방법
JP2007096178A (ja) * 2005-09-30 2007-04-12 Toshiba Corp 半導体装置およびその製造方法
JP2008078390A (ja) * 2006-09-21 2008-04-03 Fujitsu Ltd 半導体装置およびその製造方法
JP5109395B2 (ja) * 2007-02-14 2012-12-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260600A (ja) * 1996-03-19 1997-10-03 Sharp Corp 半導体メモリ素子の製造方法
JP2002280523A (ja) * 2001-03-16 2002-09-27 Nec Corp 半導体記憶装置とその製造方法
JP2005217203A (ja) * 2004-01-29 2005-08-11 Seiko Epson Corp 配線パターンの形成方法及び強誘電体メモリの製造方法、強誘電体メモリ

Also Published As

Publication number Publication date
US20090280578A1 (en) 2009-11-12
KR20070025902A (ko) 2007-03-08
US7579641B2 (en) 2009-08-25
JP4617227B2 (ja) 2011-01-19
US8815612B2 (en) 2014-08-26
US8216857B2 (en) 2012-07-10
JP2007067294A (ja) 2007-03-15
US20120309112A1 (en) 2012-12-06
CN100511684C (zh) 2009-07-08
US20070045688A1 (en) 2007-03-01
CN1925160A (zh) 2007-03-07

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