KR100653797B1 - 반도체 장치의 제조 방법 - Google Patents
반도체 장치의 제조 방법 Download PDFInfo
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- KR100653797B1 KR100653797B1 KR1019990049144A KR19990049144A KR100653797B1 KR 100653797 B1 KR100653797 B1 KR 100653797B1 KR 1019990049144 A KR1019990049144 A KR 1019990049144A KR 19990049144 A KR19990049144 A KR 19990049144A KR 100653797 B1 KR100653797 B1 KR 100653797B1
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- South Korea
- Prior art keywords
- polishing
- metal layer
- abrasive
- layer
- rate
- Prior art date
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- 239000002184 metal Substances 0.000 claims abstract description 336
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- 230000007797 corrosion Effects 0.000 abstract description 27
- 238000005260 corrosion Methods 0.000 abstract description 27
- 230000002829 reductive effect Effects 0.000 abstract description 19
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- 229910052721 tungsten Inorganic materials 0.000 description 20
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 19
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- 239000010936 titanium Substances 0.000 description 19
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 19
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- 239000007788 liquid Substances 0.000 description 18
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- 229910003480 inorganic solid Inorganic materials 0.000 description 14
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- 238000002955 isolation Methods 0.000 description 2
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- 238000002474 experimental method Methods 0.000 description 1
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- 239000004310 lactic acid Substances 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- XNGIFLGASWRNHJ-UHFFFAOYSA-L phthalate(2-) Chemical compound [O-]C(=O)C1=CC=CC=C1C([O-])=O XNGIFLGASWRNHJ-UHFFFAOYSA-L 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 239000004584 polyacrylic acid Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- FJWLWIRHZOHPIY-UHFFFAOYSA-N potassium;hydroiodide Chemical compound [K].I FJWLWIRHZOHPIY-UHFFFAOYSA-N 0.000 description 1
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- 238000003825 pressing Methods 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
- 239000001384 succinic acid Substances 0.000 description 1
- 235000011044 succinic acid Nutrition 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
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- 239000002699 waste material Substances 0.000 description 1
- 239000002351 wastewater Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
또한, 하층 금속막(32)인 티탄의 연마 속도는 구리 절연층(30)의 연마 속도와 같은 정도가 실제로는 이용되고 있다. 그 상한이 되는 비율은 구체적으로는 0058란에 연마제로서 요오드산 칼륨을 이용한 경우, 티탄의 연마 속도가 120㎚/min, 산화막의 연마 속도가 25㎚/min이라고 기재되어 있다.
따라서, 티탄의 연마 속도가 산화막의 연마 속도의 4.8배(120÷25=4.8)가 된다. 이 연마제는 제1 연마제로서 사용할 수 있지만, 제2 연마제에는 별도의 연마제가 필요한 것이 진술되고 있다. 따라서, 제2 연마제에는 하층 금속층의 연마 속도는 절연층과 거의 동등한 것이 바람직하고, 4.8배보다도 낮아야만 한다는 것을 알 수 있다. 그러나, 대면적의 배선 기판 내의 연마 속도 분포나 복수의 배선 기판 간의 구조나 연마 속도의 변동 등을 고려하여 수십% 정도의 과잉 연마를 행하면, 기판 내에서는 홈깊이의 변동, 나아가서는 배선 두께의 차이에 따른 저항 변동이 커지게 되므로, 같은 정도 혹은 넉넉잡아서 4배 이내의 연마 속도의 선택성의 값은 충분하다고는 할 수 없다.
낮은 저항의 배선을 배선 기판 전면에 걸쳐 균일하게 형성하기 위해서는 절연층(31)의 두께를 줄이는 일 없이, 배선 기판 전면의 소정 부분 예를 들면 배선회로나 소자가 형성되어 있는 영역에 걸쳐 상층 및 하층의 금속층을 재현성좋고 균일하게 제거하는 것이 요구된다.
본 발명은 이러한 점에 감안하여 이루어진 것으로, 상층의 금속층과 장벽 효과를 갖는 하층의 금속층으로 이루어지는 적층의 다마신 배선을 형성할 때의 배선 형상의 열화를 억제하면서 수율이나 안정성좋게 제1 합금층을 제거하여 배선을 형성하는 것을 목적으로 한다.
또, 상기 특개평 10-214834호에는 연마의 화학적 에칭에 관한 기술은 없어서 연마 공정에서 얼마만큼 화학적으로 에칭이 진행되고 있는지 도무지 불명확하다.
이러한 연마 과정의 시간적인 변화를 도 4를 이용하여 설명한다. 간단하게 하기 위해서, 상층 금속과 하층 금속과의 2층으로 이루어지는 경우에 대하여 진술한다. 제1 연마에서는 상층 금속층은 빠르게 연마된다. 그리고, 도 4의 (a)와 같이 하층 금속층의 연마 속도가 낮은 경우는 하층 금속층의 거의 표면에서 실질적으로 연마가 정지된다. 과잉 연마를 행하여도 거의 영향은 없다. 다음에 제2 연마를 행한다. 절연층의 연마 속도는 하층 금속층의 연마 속도보다도 현저하게 낮기 때문에, 연마 속도 최저(Min)의 부분의 연마가 종료 후, 또한 10 내지 20% 정도의 과잉 연마를 행하여도 깊이 변동이 생기는 최대 부분의 절연층의 연마량은 매우 근소하다. 그 깊이 변동은 연마 속도의 비가 클수록 작아진다. 또한, 하층 금속층의 연마 속도도 상층 금속층의 연마 속도와 같은 정도인 경우는 도 4의 (b)와 같이 거의 과잉 연마를 행하지 않고서 절연층의 표면에서 제1 연마를 거의 종료시킨다. 여기서는 연마 속도가 평균적인 부분에서 연마가 종료한 경우에 제1 연마를 종료시켜도 좋다. 연마 속도 최대(Max) 부분에서는 절연층이 약간 연마되지만 그 값은 상층 혹은 하층의 금속층의 연마 속도의 절연층의 연마 속도에 대한 비에 거의 반비례하여 작게 억제된다. 다음에 제2 연마에 의해서 하층 금속층을 제거한다. 연마 속도 최소(Min) 부분의 연마 종료로부터 또한 10 내지 20% 정도의 과잉 연마를 행하여도 좋다. 이 경우, 도 5의 경우보다는 약간 깊이 변동이 늘지만, 절연층의 연마 속도가 하층 금속층의 연마 속도보다도 현저하게 낮기 때문에, 종래 기술에 의하면 훨씬 적어진다. 현저한 경우는 디싱이나 부식을 포함시킨 깊이 변동은 종래의 1/3 내지 1/5 정도까지 개선된다.
Claims (46)
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- 반도체 장치의 제조 방법에 있어서,기판 상에 비어 홀이 설치된 절연막을 형성하는 공정;상기 비어 홀 내측으로부터 상기 비어 홀 외측으로 연장하여 제1 금속막을 형성하는 공정;상기 제1 금속막 상에 제2 금속막을 형성하는 공정;상기 제2 금속막을 연마하는 공정; 및상기 제1 금속막을, 상기 제2 금속막에 대한 에칭 속도의 5배 이상의 연마 속도로 연마하는 공정을 포함하는 반도체 장치의 제조 방법.
- 제14항에 있어서, 상기 제1 금속막을 연마하는 공정은 산성 영역에서 행해지는 반도체 장치의 제조 방법.
- 제14항에 있어서, 상기 제2 금속막을 연마하는 공정은 산성 영역에서 행해지는 반도체 장치의 제조 방법.
- 제14항에 있어서, 상기 제1 금속막은 적어도 2층의 금속막을 포함하는 반도체 장치의 제조 방법.
- 반도체 장치의 제조 방법에 있어서,기판 상에 비어 홀이 설치된 절연막을 형성하는 공정;상기 비어 홀 내측으로부터 상기 비어 홀 외측으로 연장하여 제1 금속막을 형성하는 공정;상기 제1 금속막 상에 제2 금속막을 형성하는 공정;상기 제2 금속막을 연마하는 공정; 및상기 제1 금속막을, 상기 제2 금속막에 대한 에칭 속도의 10배 이상의 연마 속도로 연마하는 공정을 포함하는 반도체 장치의 제조 방법.
- 반도체 장치의 제조 방법에 있어서,기판 상에 비어 홀이 설치된 절연막을 형성하는 공정;상기 비어 홀 내측으로부터 상기 비어 홀 외측으로 연장하여 제1 금속막을 형성하는 공정;상기 제1 금속막 상에 제2 금속막을 형성하는 공정;상기 제2 금속막을 연마하는 공정; 및상기 제1 금속막을, 상기 제2 금속막에 대한 에칭 속도의 15배 이상의 연마 속도로 연마하는 공정을 포함하는 반도체 장치의 제조 방법.
- 제19항에 있어서, 상기 기판은 직경이 150㎜ 이상인 반도체 장치의 제조 방법.
- 반도체 장치의 제조 방법에 있어서,기판 상에 비어 홀이 설치된 절연막을 형성하는 공정;상기 비어 홀 내측으로부터 상기 비어 홀 외측으로 연장하여 제1 금속막을 형성하는 공정;상기 제1 금속막 상에 제2 금속막을 형성하는 공정;상기 제2 금속막을, 상기 제2 금속막에 대한 에칭 속도의 적어도 5배 이상의 연마 속도로 연마 슬러리에 의해 연마하는 공정; 및상기 제1 금속막을 연마하는 공정을 포함하는 반도체 장치의 제조 방법.
- 제21항에 있어서, 상기 제1 금속막은 상기 제2 금속막에 대한 에칭 속도의 5배 이상의 연마 속도로 연마되는 반도체 장치의 제조 방법.
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- 반도체 장치의 제조 방법에 있어서,절연막 내에 비어 홀을 형성하는 공정;상기 비어 홀이 형성된 절연막 상에, 상기 비어 홀 내측으로부터 상기 비어 홀 외측에 걸쳐 제1 도전막을 형성하는 공정;상기 제1 도전막 상에 제2 도전막을 형성하는 공정;상기 제2 도전막을 제1 플래튼(定盤)을 이용하여 연마하는 공정; 및상기 비어 홀 각각 내에 매립된 제1 도전막을 제2 플래튼을 이용하여, 상기 비어 홀 내에 형성된 상기 제2 도전막의 높이보다도 커지도록 연마하는 공정을 포함하는 반도체 장치의 제조 방법.
- 제42항에 있어서, 상기 제1 플래튼 및 상기 제2 플래튼은 서로 다른 반도체 장치의 제조 방법.
- 제42항에 있어서, 상기 제1 플래튼 이용하여 연마하는 공정과, 상기 제2 플래튼을 이용하여 연마하는 공정 중 적어도 한 쪽은 연마 분체(abrasive powder)를 포함하는 레진 본드 지석(resin bonded whetstone)을 사용하는 반도체 장치의 제조 방법.
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Also Published As
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US20020025605A1 (en) | 2002-02-28 |
TW452877B (en) | 2001-09-01 |
US6326299B1 (en) | 2001-12-04 |
US20030003713A1 (en) | 2003-01-02 |
US6638854B2 (en) | 2003-10-28 |
JP4095731B2 (ja) | 2008-06-04 |
JP2000150435A (ja) | 2000-05-30 |
KR20000035287A (ko) | 2000-06-26 |
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