KR100646209B1 - 반도체 집적회로장치 - Google Patents
반도체 집적회로장치 Download PDFInfo
- Publication number
- KR100646209B1 KR100646209B1 KR1019990034761A KR19990034761A KR100646209B1 KR 100646209 B1 KR100646209 B1 KR 100646209B1 KR 1019990034761 A KR1019990034761 A KR 1019990034761A KR 19990034761 A KR19990034761 A KR 19990034761A KR 100646209 B1 KR100646209 B1 KR 100646209B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- power supply
- voltage
- region
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24160798A JP4079522B2 (ja) | 1998-08-27 | 1998-08-27 | 半導体集積回路装置 |
| JP98-241607 | 1998-08-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000017436A KR20000017436A (ko) | 2000-03-25 |
| KR100646209B1 true KR100646209B1 (ko) | 2006-11-17 |
Family
ID=17076844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990034761A Expired - Lifetime KR100646209B1 (ko) | 1998-08-27 | 1999-08-21 | 반도체 집적회로장치 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6411160B1 (enExample) |
| JP (1) | JP4079522B2 (enExample) |
| KR (1) | KR100646209B1 (enExample) |
| TW (1) | TW421883B (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002016238A (ja) * | 2000-06-29 | 2002-01-18 | Mitsubishi Electric Corp | 半導体装置 |
| KR100400311B1 (ko) * | 2001-06-29 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 신호 지연 제어 장치 |
| US6664589B2 (en) * | 2001-08-30 | 2003-12-16 | Micron Technology, Inc. | Technique to control tunneling currents in DRAM capacitors, cells, and devices |
| JP3786608B2 (ja) * | 2002-01-28 | 2006-06-14 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| US7055069B2 (en) * | 2002-08-23 | 2006-05-30 | Infineon Technologies Ag | Spare input/output buffer |
| US6969909B2 (en) * | 2002-12-20 | 2005-11-29 | Vlt, Inc. | Flip chip FET device |
| US7615822B1 (en) | 2002-12-23 | 2009-11-10 | Volterra Semiconductor Corporation | Diffused drain transistor |
| US7038917B2 (en) * | 2002-12-27 | 2006-05-02 | Vlt, Inc. | Low loss, high density array interconnection |
| FR2853475B1 (fr) * | 2003-04-01 | 2005-07-08 | Atmel Nantes Sa | Circuit integre delivrant des niveaux logiques a une tension independante de la tension d'alimentation, sans regulateur associe pour la partie puissance, et module de communication correspondant |
| US7074659B2 (en) * | 2003-11-13 | 2006-07-11 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor |
| US7220633B2 (en) * | 2003-11-13 | 2007-05-22 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET |
| US7163856B2 (en) | 2003-11-13 | 2007-01-16 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
| JP4364226B2 (ja) * | 2006-09-21 | 2009-11-11 | 株式会社東芝 | 半導体集積回路 |
| US7663953B2 (en) * | 2007-03-12 | 2010-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for high speed sensing for extra low voltage DRAM |
| US7663908B2 (en) * | 2007-03-12 | 2010-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for increasing retention time in DRAM |
| US8830784B2 (en) | 2011-10-14 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative word line driver for semiconductor memories |
| US8624632B2 (en) | 2012-03-29 | 2014-01-07 | International Business Machines Corporation | Sense amplifier-type latch circuits with static bias current for enhanced operating frequency |
| US9196375B2 (en) | 2013-07-05 | 2015-11-24 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
| US20200350263A1 (en) * | 2019-04-30 | 2020-11-05 | Nxp B.V. | Semiconductor devices with security features |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05174578A (ja) * | 1991-12-24 | 1993-07-13 | Mitsubishi Electric Corp | 半導体装置 |
| KR970029835A (ko) * | 1995-11-09 | 1997-06-26 | 가나이 츠토무 | 셀어레이상에 전원 및 신호버스가 메시형상으로 배치된 시스템 |
| JP2000049305A (ja) * | 1998-07-28 | 2000-02-18 | Hitachi Ltd | 半導体記憶装置 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2919365B2 (ja) * | 1996-06-27 | 1999-07-12 | 日本電気アイシーマイコンシステム株式会社 | Mosトランジスタの容量設計方法 |
-
1998
- 1998-08-27 JP JP24160798A patent/JP4079522B2/ja not_active Expired - Fee Related
-
1999
- 1999-07-13 TW TW088111875A patent/TW421883B/zh not_active IP Right Cessation
- 1999-08-18 US US09/376,470 patent/US6411160B1/en not_active Expired - Lifetime
- 1999-08-21 KR KR1019990034761A patent/KR100646209B1/ko not_active Expired - Lifetime
-
2002
- 2002-05-13 US US10/142,897 patent/US6518835B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05174578A (ja) * | 1991-12-24 | 1993-07-13 | Mitsubishi Electric Corp | 半導体装置 |
| KR970029835A (ko) * | 1995-11-09 | 1997-06-26 | 가나이 츠토무 | 셀어레이상에 전원 및 신호버스가 메시형상으로 배치된 시스템 |
| JP2000049305A (ja) * | 1998-07-28 | 2000-02-18 | Hitachi Ltd | 半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4079522B2 (ja) | 2008-04-23 |
| US6411160B1 (en) | 2002-06-25 |
| US6518835B2 (en) | 2003-02-11 |
| JP2000077623A (ja) | 2000-03-14 |
| KR20000017436A (ko) | 2000-03-25 |
| US20020130714A1 (en) | 2002-09-19 |
| TW421883B (en) | 2001-02-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19990821 |
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| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20040820 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19990821 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20060202 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20060809 |
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| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20061108 Patent event code: PR07011E01D |
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| PR1002 | Payment of registration fee |
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