KR100572036B1 - Cvd 장벽층을 갖는 보더리스 비아들 - Google Patents

Cvd 장벽층을 갖는 보더리스 비아들 Download PDF

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Publication number
KR100572036B1
KR100572036B1 KR1020007002350A KR20007002350A KR100572036B1 KR 100572036 B1 KR100572036 B1 KR 100572036B1 KR 1020007002350 A KR1020007002350 A KR 1020007002350A KR 20007002350 A KR20007002350 A KR 20007002350A KR 100572036 B1 KR100572036 B1 KR 100572036B1
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Prior art keywords
layer
metal layer
metal structure
titanium nitride
semiconductor device
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Expired - Fee Related
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Korean (ko)
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KR20010023696A (ko
Inventor
첸로버트씨.
그린로데이비드씨.
아이코포니존에이.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Publication of KR20010023696A publication Critical patent/KR20010023696A/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020007002350A 1997-09-05 1998-08-31 Cvd 장벽층을 갖는 보더리스 비아들 Expired - Fee Related KR100572036B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/924,131 1997-09-05
US08/924,131 US5969425A (en) 1997-09-05 1997-09-05 Borderless vias with CVD barrier layer
PCT/US1998/018012 WO1999013501A1 (en) 1997-09-05 1998-08-31 Borderless vias with cvd barrier layer

Publications (2)

Publication Number Publication Date
KR20010023696A KR20010023696A (ko) 2001-03-26
KR100572036B1 true KR100572036B1 (ko) 2006-04-18

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KR1020007002350A Expired - Fee Related KR100572036B1 (ko) 1997-09-05 1998-08-31 Cvd 장벽층을 갖는 보더리스 비아들

Country Status (5)

Country Link
US (2) US5969425A (enExample)
EP (1) EP1018152A1 (enExample)
JP (1) JP2001516153A (enExample)
KR (1) KR100572036B1 (enExample)
WO (1) WO1999013501A1 (enExample)

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US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
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US7645704B2 (en) * 2003-09-17 2010-01-12 Texas Instruments Incorporated Methods and apparatus of etch process control in fabrications of microstructures
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US7317253B2 (en) * 2005-04-25 2008-01-08 Sony Corporation Cobalt tungsten phosphate used to fill voids arising in a copper metallization process
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KR101315880B1 (ko) 2008-07-23 2013-10-08 삼성전자주식회사 금속 배선 구조물 및 그 제조 방법
KR20120083142A (ko) * 2011-01-17 2012-07-25 삼성전자주식회사 반도체 장치 및 반도체 장치의 형성 방법
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KR102717808B1 (ko) * 2016-11-30 2024-10-15 엘지디스플레이 주식회사 두 개의 전극들 사이에 위치하는 다수의 절연막들을 포함하는 디스플레이 장치
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Also Published As

Publication number Publication date
US5969425A (en) 1999-10-19
US6159851A (en) 2000-12-12
WO1999013501A1 (en) 1999-03-18
EP1018152A1 (en) 2000-07-12
KR20010023696A (ko) 2001-03-26
JP2001516153A (ja) 2001-09-25

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