KR100572036B1 - Cvd 장벽층을 갖는 보더리스 비아들 - Google Patents
Cvd 장벽층을 갖는 보더리스 비아들 Download PDFInfo
- Publication number
- KR100572036B1 KR100572036B1 KR1020007002350A KR20007002350A KR100572036B1 KR 100572036 B1 KR100572036 B1 KR 100572036B1 KR 1020007002350 A KR1020007002350 A KR 1020007002350A KR 20007002350 A KR20007002350 A KR 20007002350A KR 100572036 B1 KR100572036 B1 KR 100572036B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- metal layer
- metal structure
- titanium nitride
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/924,131 | 1997-09-05 | ||
| US08/924,131 US5969425A (en) | 1997-09-05 | 1997-09-05 | Borderless vias with CVD barrier layer |
| PCT/US1998/018012 WO1999013501A1 (en) | 1997-09-05 | 1998-08-31 | Borderless vias with cvd barrier layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010023696A KR20010023696A (ko) | 2001-03-26 |
| KR100572036B1 true KR100572036B1 (ko) | 2006-04-18 |
Family
ID=25449751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020007002350A Expired - Fee Related KR100572036B1 (ko) | 1997-09-05 | 1998-08-31 | Cvd 장벽층을 갖는 보더리스 비아들 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5969425A (enExample) |
| EP (1) | EP1018152A1 (enExample) |
| JP (1) | JP2001516153A (enExample) |
| KR (1) | KR100572036B1 (enExample) |
| WO (1) | WO1999013501A1 (enExample) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849471B2 (en) * | 2003-03-28 | 2005-02-01 | Reflectivity, Inc. | Barrier layers for microelectromechanical systems |
| US6074943A (en) * | 1997-04-16 | 2000-06-13 | Texas Instruments Incorporated | Sidewalls for guiding the via etch |
| US6114766A (en) * | 1997-12-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Integrated circuit with metal features presenting a larger landing area for vias |
| US6087724A (en) * | 1997-12-18 | 2000-07-11 | Advanced Micro Devices, Inc. | HSQ with high plasma etching resistance surface for borderless vias |
| US7001713B2 (en) * | 1998-04-18 | 2006-02-21 | United Microelectronics, Corp. | Method of forming partial reverse active mask |
| US6048787A (en) * | 1998-09-08 | 2000-04-11 | Winbond Electronics Corp. | Borderless contacts for dual-damascene interconnect process |
| US6329282B1 (en) * | 1998-09-11 | 2001-12-11 | Texas Instruments Incorporated | Method of improving the texture of aluminum metallization for tungsten etch back processing |
| JP3606095B2 (ja) * | 1998-10-06 | 2005-01-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| US6312830B1 (en) | 1999-09-02 | 2001-11-06 | Intel Corporation | Method and an apparatus for forming an under bump metallization structure |
| JP2001127088A (ja) * | 1999-10-27 | 2001-05-11 | Mitsubishi Electric Corp | 半導体装置 |
| US6245631B1 (en) * | 1999-12-06 | 2001-06-12 | Micron Technology, Inc. | Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line |
| US6337274B1 (en) | 1999-12-06 | 2002-01-08 | Micron Technology, Inc. | Methods of forming buried bit line memory circuitry |
| US6531389B1 (en) * | 1999-12-20 | 2003-03-11 | Taiwan Semiconductor Manufacturing Company | Method for forming incompletely landed via with attenuated contact resistance |
| US6544882B1 (en) * | 2000-01-13 | 2003-04-08 | Taiwan Semiconductor Manufacturing Company | Method to improve reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers in integrated circuits |
| US6303486B1 (en) * | 2000-01-28 | 2001-10-16 | Advanced Micro Devices, Inc. | Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal |
| WO2002021593A2 (en) * | 2000-09-08 | 2002-03-14 | Applied Materials, Inc. | Method of forming titanium nitride (tin) films using metal-organic chemical vapor deposition (mocvd) |
| US6294463B1 (en) * | 2000-09-13 | 2001-09-25 | Vanguard International Semiconductor Corp. | Method for manufacturing diffusion barrier layer |
| JP3408527B2 (ja) | 2000-10-26 | 2003-05-19 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| US6613664B2 (en) * | 2000-12-28 | 2003-09-02 | Infineon Technologies Ag | Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices |
| US6626187B2 (en) * | 2001-02-07 | 2003-09-30 | Promos Technologies Inc. | Method of reconditioning reaction chamber |
| TW544916B (en) * | 2002-01-10 | 2003-08-01 | Winbond Electronics Corp | Memory device having complex type contact plug and its manufacturing method |
| US20030219459A1 (en) * | 2002-01-18 | 2003-11-27 | Cytos Biotechnology Ag | Prion protein carrier-conjugates |
| US6770566B1 (en) | 2002-03-06 | 2004-08-03 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures, and articles and devices formed thereby |
| US6806579B2 (en) * | 2003-02-11 | 2004-10-19 | Infineon Technologies Ag | Robust via structure and method |
| US7645704B2 (en) * | 2003-09-17 | 2010-01-12 | Texas Instruments Incorporated | Methods and apparatus of etch process control in fabrications of microstructures |
| DE102004031878B3 (de) * | 2004-07-01 | 2005-10-06 | Epcos Ag | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
| JP2006156716A (ja) * | 2004-11-30 | 2006-06-15 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| KR100668833B1 (ko) * | 2004-12-17 | 2007-01-16 | 주식회사 하이닉스반도체 | 반도체소자의 캐패시터 제조방법 |
| KR100596487B1 (ko) * | 2005-04-12 | 2006-07-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US7317253B2 (en) * | 2005-04-25 | 2008-01-08 | Sony Corporation | Cobalt tungsten phosphate used to fill voids arising in a copper metallization process |
| KR100842517B1 (ko) * | 2005-10-06 | 2008-07-01 | 삼성전자주식회사 | 통신 시스템에서 단말기의 전력 안정화 장치 |
| US20090202807A1 (en) * | 2006-06-22 | 2009-08-13 | National Kuniversity Corporation Kitami Institue Of Technology | Method for producing metal nitride film, oxide film, metal carbide film or composite film of them, and production apparatus therefor |
| US7675162B2 (en) * | 2006-10-03 | 2010-03-09 | Innovative Micro Technology | Interconnect structure using through wafer vias and method of fabrication |
| KR100815938B1 (ko) * | 2006-10-20 | 2008-03-21 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
| US7859113B2 (en) * | 2007-02-27 | 2010-12-28 | International Business Machines Corporation | Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method |
| US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
| DE102007020263B4 (de) * | 2007-04-30 | 2013-12-12 | Infineon Technologies Ag | Verkrallungsstruktur |
| KR101315880B1 (ko) | 2008-07-23 | 2013-10-08 | 삼성전자주식회사 | 금속 배선 구조물 및 그 제조 방법 |
| KR20120083142A (ko) * | 2011-01-17 | 2012-07-25 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 형성 방법 |
| US9034664B2 (en) * | 2012-05-16 | 2015-05-19 | International Business Machines Corporation | Method to resolve hollow metal defects in interconnects |
| KR102717808B1 (ko) * | 2016-11-30 | 2024-10-15 | 엘지디스플레이 주식회사 | 두 개의 전극들 사이에 위치하는 다수의 절연막들을 포함하는 디스플레이 장치 |
| US11133218B1 (en) * | 2020-01-23 | 2021-09-28 | Tae Young Lee | Semiconductor apparatus having through silicon via structure and manufacturing method thereof |
| US12438084B2 (en) * | 2021-12-13 | 2025-10-07 | International Business Machines Corporation | Dual-metal ultra thick metal (UTM) structure |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143425A (ja) * | 1988-11-24 | 1990-06-01 | Sony Corp | A1又はa1合金膜のテーパーエッチング方法 |
| JP2660359B2 (ja) * | 1991-01-30 | 1997-10-08 | 三菱電機株式会社 | 半導体装置 |
| JPH0823028A (ja) * | 1994-07-05 | 1996-01-23 | Oki Electric Ind Co Ltd | 多層配線を有する半導体素子及びその製造方法 |
| US5470790A (en) * | 1994-10-17 | 1995-11-28 | Intel Corporation | Via hole profile and method of fabrication |
| US5619072A (en) * | 1995-02-09 | 1997-04-08 | Advanced Micro Devices, Inc. | High density multi-level metallization and interconnection structure |
| JP2663902B2 (ja) * | 1995-03-17 | 1997-10-15 | 日本電気株式会社 | 微細トレンチの埋め込み方法、微細電極の製造方法、微細ホールの埋め込み方法、及び微細金属配線の製造方法 |
| KR100218728B1 (ko) * | 1995-11-01 | 1999-09-01 | 김영환 | 반도체 소자의 금속 배선 제조방법 |
| JPH09213801A (ja) * | 1996-01-29 | 1997-08-15 | Sony Corp | 接続孔の形成工程を有する半導体装置の製造方法 |
| JPH09219450A (ja) * | 1996-02-09 | 1997-08-19 | Denso Corp | 半導体装置の製造方法 |
| JPH09232284A (ja) * | 1996-02-22 | 1997-09-05 | Hitachi Ltd | Al配線のエッチング方法及びエッチング装置 |
| JPH09237830A (ja) * | 1996-02-28 | 1997-09-09 | Sony Corp | 半導体装置の製造方法 |
| US5808364A (en) * | 1997-04-08 | 1998-09-15 | International Business Machines Corporation | Interconnects using metal spacers |
-
1997
- 1997-09-05 US US08/924,131 patent/US5969425A/en not_active Expired - Lifetime
-
1998
- 1998-08-31 JP JP2000511189A patent/JP2001516153A/ja active Pending
- 1998-08-31 KR KR1020007002350A patent/KR100572036B1/ko not_active Expired - Fee Related
- 1998-08-31 WO PCT/US1998/018012 patent/WO1999013501A1/en not_active Ceased
- 1998-08-31 EP EP98943479A patent/EP1018152A1/en not_active Ceased
-
1999
- 1999-04-21 US US09/295,362 patent/US6159851A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5969425A (en) | 1999-10-19 |
| US6159851A (en) | 2000-12-12 |
| WO1999013501A1 (en) | 1999-03-18 |
| EP1018152A1 (en) | 2000-07-12 |
| KR20010023696A (ko) | 2001-03-26 |
| JP2001516153A (ja) | 2001-09-25 |
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St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20160412 |
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| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |