KR100470371B1 - 반도체 기억 장치 - Google Patents

반도체 기억 장치 Download PDF

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Publication number
KR100470371B1
KR100470371B1 KR10-2002-0079761A KR20020079761A KR100470371B1 KR 100470371 B1 KR100470371 B1 KR 100470371B1 KR 20020079761 A KR20020079761 A KR 20020079761A KR 100470371 B1 KR100470371 B1 KR 100470371B1
Authority
KR
South Korea
Prior art keywords
block
address
circuit
signal
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2002-0079761A
Other languages
English (en)
Korean (ko)
Other versions
KR20030051317A (ko
Inventor
다우라다다유끼
아쯔미시게루
마에다슈지
Original Assignee
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 도시바 filed Critical 가부시끼가이샤 도시바
Publication of KR20030051317A publication Critical patent/KR20030051317A/ko
Application granted granted Critical
Publication of KR100470371B1 publication Critical patent/KR100470371B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Read Only Memory (AREA)
KR10-2002-0079761A 2001-12-14 2002-12-13 반도체 기억 장치 Expired - Fee Related KR100470371B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001381412A JP2003187591A (ja) 2001-12-14 2001-12-14 半導体記憶装置
JPJP-P-2001-00381412 2001-12-14

Publications (2)

Publication Number Publication Date
KR20030051317A KR20030051317A (ko) 2003-06-25
KR100470371B1 true KR100470371B1 (ko) 2005-02-11

Family

ID=19187333

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0079761A Expired - Fee Related KR100470371B1 (ko) 2001-12-14 2002-12-13 반도체 기억 장치

Country Status (6)

Country Link
US (1) US6707733B2 (enExample)
EP (1) EP1320105B1 (enExample)
JP (1) JP2003187591A (enExample)
KR (1) KR100470371B1 (enExample)
CN (1) CN1267997C (enExample)
DE (1) DE60215291T2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4235122B2 (ja) * 2004-02-06 2009-03-11 シャープ株式会社 半導体記憶装置及び半導体記憶装置のテスト方法
US7085180B2 (en) * 2004-02-12 2006-08-01 International Business Machines Corporation Method and structure for enabling a redundancy allocation during a multi-bank operation
JP4722123B2 (ja) * 2005-02-23 2011-07-13 スパンション エルエルシー 記憶装置の冗長設定方法、および記憶装置
US7447066B2 (en) * 2005-11-08 2008-11-04 Sandisk Corporation Memory with retargetable memory cell redundancy
JP5131348B2 (ja) * 2008-03-19 2013-01-30 富士通セミコンダクター株式会社 半導体メモリ、システム、半導体メモリの動作方法および半導体メモリの製造方法
KR101600280B1 (ko) 2014-05-28 2016-03-21 주식회사 피델릭스 사용중에 발생되는 결함을 효율적으로 리페어할 수 있는 플래시 메모리 장치 및 그의 리페어 방법
US20160012916A1 (en) * 2014-07-10 2016-01-14 Kabushiki Kaisha Toshiba Semiconductor memory device and memory system
US9741421B1 (en) * 2016-04-05 2017-08-22 Micron Technology, Inc. Refresh circuitry
JP7171286B2 (ja) * 2018-07-20 2022-11-15 ラピスセミコンダクタ株式会社 半導体メモリ装置
JP7112904B2 (ja) * 2018-07-20 2022-08-04 ラピスセミコンダクタ株式会社 半導体メモリのテスト方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3019869B2 (ja) * 1990-10-16 2000-03-13 富士通株式会社 半導体メモリ
JP2001052495A (ja) * 1999-06-03 2001-02-23 Toshiba Corp 半導体メモリ
JP2002015593A (ja) * 2000-06-27 2002-01-18 Toshiba Corp 半導体記憶装置
US6552939B1 (en) * 2001-10-15 2003-04-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having disturb test circuit

Also Published As

Publication number Publication date
CN1438707A (zh) 2003-08-27
KR20030051317A (ko) 2003-06-25
DE60215291D1 (de) 2006-11-23
JP2003187591A (ja) 2003-07-04
EP1320105B1 (en) 2006-10-11
EP1320105A2 (en) 2003-06-18
DE60215291T2 (de) 2007-05-10
US20030117867A1 (en) 2003-06-26
EP1320105A3 (en) 2005-03-09
CN1267997C (zh) 2006-08-02
US6707733B2 (en) 2004-03-16

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