CN1267997C - 半导体存储器件 - Google Patents

半导体存储器件 Download PDF

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Publication number
CN1267997C
CN1267997C CNB021560714A CN02156071A CN1267997C CN 1267997 C CN1267997 C CN 1267997C CN B021560714 A CNB021560714 A CN B021560714A CN 02156071 A CN02156071 A CN 02156071A CN 1267997 C CN1267997 C CN 1267997C
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CN
China
Prior art keywords
address
mentioned
circuit
block
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB021560714A
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English (en)
Chinese (zh)
Other versions
CN1438707A (zh
Inventor
田浦忠行
渥美滋
前田修治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1438707A publication Critical patent/CN1438707A/zh
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Publication of CN1267997C publication Critical patent/CN1267997C/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Read Only Memory (AREA)
CNB021560714A 2001-12-14 2002-12-13 半导体存储器件 Expired - Fee Related CN1267997C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001381412A JP2003187591A (ja) 2001-12-14 2001-12-14 半導体記憶装置
JP2001381412 2001-12-14

Publications (2)

Publication Number Publication Date
CN1438707A CN1438707A (zh) 2003-08-27
CN1267997C true CN1267997C (zh) 2006-08-02

Family

ID=19187333

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021560714A Expired - Fee Related CN1267997C (zh) 2001-12-14 2002-12-13 半导体存储器件

Country Status (6)

Country Link
US (1) US6707733B2 (enExample)
EP (1) EP1320105B1 (enExample)
JP (1) JP2003187591A (enExample)
KR (1) KR100470371B1 (enExample)
CN (1) CN1267997C (enExample)
DE (1) DE60215291T2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4235122B2 (ja) * 2004-02-06 2009-03-11 シャープ株式会社 半導体記憶装置及び半導体記憶装置のテスト方法
US7085180B2 (en) * 2004-02-12 2006-08-01 International Business Machines Corporation Method and structure for enabling a redundancy allocation during a multi-bank operation
JP4722123B2 (ja) * 2005-02-23 2011-07-13 スパンション エルエルシー 記憶装置の冗長設定方法、および記憶装置
US7447066B2 (en) * 2005-11-08 2008-11-04 Sandisk Corporation Memory with retargetable memory cell redundancy
JP5131348B2 (ja) * 2008-03-19 2013-01-30 富士通セミコンダクター株式会社 半導体メモリ、システム、半導体メモリの動作方法および半導体メモリの製造方法
KR101600280B1 (ko) 2014-05-28 2016-03-21 주식회사 피델릭스 사용중에 발생되는 결함을 효율적으로 리페어할 수 있는 플래시 메모리 장치 및 그의 리페어 방법
US20160012916A1 (en) * 2014-07-10 2016-01-14 Kabushiki Kaisha Toshiba Semiconductor memory device and memory system
US9741421B1 (en) * 2016-04-05 2017-08-22 Micron Technology, Inc. Refresh circuitry
JP7171286B2 (ja) * 2018-07-20 2022-11-15 ラピスセミコンダクタ株式会社 半導体メモリ装置
JP7112904B2 (ja) * 2018-07-20 2022-08-04 ラピスセミコンダクタ株式会社 半導体メモリのテスト方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3019869B2 (ja) * 1990-10-16 2000-03-13 富士通株式会社 半導体メモリ
JP2001052495A (ja) * 1999-06-03 2001-02-23 Toshiba Corp 半導体メモリ
JP2002015593A (ja) * 2000-06-27 2002-01-18 Toshiba Corp 半導体記憶装置
US6552939B1 (en) * 2001-10-15 2003-04-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having disturb test circuit

Also Published As

Publication number Publication date
CN1438707A (zh) 2003-08-27
KR20030051317A (ko) 2003-06-25
DE60215291D1 (de) 2006-11-23
JP2003187591A (ja) 2003-07-04
EP1320105B1 (en) 2006-10-11
EP1320105A2 (en) 2003-06-18
DE60215291T2 (de) 2007-05-10
US20030117867A1 (en) 2003-06-26
EP1320105A3 (en) 2005-03-09
KR100470371B1 (ko) 2005-02-11
US6707733B2 (en) 2004-03-16

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Legal Events

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170802

Address after: Tokyo, Japan

Patentee after: Toshiba Storage Corporation

Address before: Tokyo, Japan, Japan

Patentee before: Toshiba Corp

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060802

Termination date: 20191213