KR100414864B1 - 디지탈카운터및디지탈pll회로 - Google Patents

디지탈카운터및디지탈pll회로 Download PDF

Info

Publication number
KR100414864B1
KR100414864B1 KR1019960038662A KR19960038662A KR100414864B1 KR 100414864 B1 KR100414864 B1 KR 100414864B1 KR 1019960038662 A KR1019960038662 A KR 1019960038662A KR 19960038662 A KR19960038662 A KR 19960038662A KR 100414864 B1 KR100414864 B1 KR 100414864B1
Authority
KR
South Korea
Prior art keywords
counter
phase
significant bit
frequency
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960038662A
Other languages
English (en)
Korean (ko)
Other versions
KR970019097A (ko
Inventor
히로시 야나기우치
Original Assignee
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Publication of KR970019097A publication Critical patent/KR970019097A/ko
Application granted granted Critical
Publication of KR100414864B1 publication Critical patent/KR100414864B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1019960038662A 1995-09-20 1996-09-06 디지탈카운터및디지탈pll회로 Expired - Fee Related KR100414864B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP95-242044 1995-09-20
JP1995-242044 1995-09-20
JP24204495A JP3538994B2 (ja) 1995-09-20 1995-09-20 ディジタルカウンタおよびディジタルｐｌｌ回路

Publications (2)

Publication Number Publication Date
KR970019097A KR970019097A (ko) 1997-04-30
KR100414864B1 true KR100414864B1 (ko) 2004-03-24

Family

ID=17083440

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960038662A Expired - Fee Related KR100414864B1 (ko) 1995-09-20 1996-09-06 디지탈카운터및디지탈pll회로

Country Status (4)

Country Link
US (1) US5896428A (enExample)
JP (1) JP3538994B2 (enExample)
KR (1) KR100414864B1 (enExample)
TW (1) TW320796B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049238A (en) * 1998-05-12 2000-04-11 Mitsubishi Denki Kabushiki Kaisha Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements
DE19850567C2 (de) * 1998-11-02 2001-02-15 Wandel & Goltermann Man Holdin Verwendung einer Schaltungsanordnung und Vorrichtung zur Messung der Signalgüte eines digitalen Nachrichtenübertragungssystems
US6760394B1 (en) * 1999-08-11 2004-07-06 Broadcom Corporation CMOS lock detect with double protection
US6708026B1 (en) * 2000-01-11 2004-03-16 Ericsson Inc. Division based local oscillator for frequency synthesis
KR100459854B1 (ko) * 2000-12-22 2004-12-03 엘지전자 주식회사 씨피유의 연산 처리 방법
GB0111300D0 (en) * 2001-05-09 2001-06-27 Mitel Knowledge Corp Method and apparatus for synchronizing slave network node to master network node
CN100349378C (zh) * 2002-04-19 2007-11-14 陈为怀 网同步可集成从时钟锁相环
US7151399B2 (en) * 2004-02-02 2006-12-19 Toshiba America Electronic Components, Inc. System and method for generating multiple clock signals
TWI274474B (en) * 2005-01-06 2007-02-21 Univ Nat Sun Yat Sen Phase-locked loop circuit and a method thereof
US20060187899A1 (en) * 2005-02-02 2006-08-24 Gemtek Systems, Inc. System of providing communication service via client representatives and the method of the same
US8369452B2 (en) * 2007-12-07 2013-02-05 Micron Technology, Inc. Majority detector apparatus, systems, and methods
KR101231743B1 (ko) * 2009-04-24 2013-02-08 한국전자통신연구원 디지털 락 검출장치 및 이를 포함하는 주파수 합성기
CN103329440B (zh) * 2010-12-29 2016-03-23 爱立信(中国)通信有限公司 相位频率检测方法
US10727847B1 (en) 2019-02-07 2020-07-28 International Business Machines Corporation Digital control of a voltage controlled oscillator frequency

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221121A (ja) * 1983-05-31 1984-12-12 Matsushita Electric Ind Co Ltd デジタルｐｌｌ回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4272729A (en) * 1979-05-10 1981-06-09 Harris Corporation Automatic pretuning of a voltage controlled oscillator in a frequency synthesizer using successive approximation
JP3329088B2 (ja) * 1994-02-16 2002-09-30 株式会社デンソー パルス発生装置，周波数可変発振装置及びｐｌｌ装置
JP2771464B2 (ja) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5651036A (en) * 1996-05-09 1997-07-22 National Semiconductor Corporation Third harmonic suppression scheme for a wave used in a phase-to-frequency converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221121A (ja) * 1983-05-31 1984-12-12 Matsushita Electric Ind Co Ltd デジタルｐｌｌ回路

Also Published As

Publication number Publication date
JPH0993120A (ja) 1997-04-04
KR970019097A (ko) 1997-04-30
TW320796B (enExample) 1997-11-21
JP3538994B2 (ja) 2004-06-14
US5896428A (en) 1999-04-20

Similar Documents

Publication Publication Date Title
JP2944607B2 (ja) ディジタルｐｌｌ回路とクロックの生成方法
US6157694A (en) Fractional frequency divider
KR100414864B1 (ko) 디지탈카운터및디지탈pll회로
US5781054A (en) Digital phase correcting apparatus
US6480047B2 (en) Reduced jitter phase lock loop using a technique multi-stage digital delay line
US5602884A (en) Digital phase locked loop
US5729179A (en) Variable Frequency Divider
EP0727877B1 (en) Fast frequency switching synthesizer
US5789985A (en) Frequency multiplying device and digitally-controlled oscillator
JPH10327071A (ja) 分数性位相同期ループコヒーレント周波数シンセサイザ
JP3179527B2 (ja) デジタル信号合成方法及び装置
JPH08505992A (ja) ジッタを防止したフェイズロックドループの周波数合成用再トリガ・オシレータ
JPS61273016A (ja) 周波数シンセサイザ−回路
EP0670635B1 (en) Phase-locked loop oscillator, and moving-average circuit, and division-ratio equalization circuit suitable for use in the same
EP1385306A1 (en) Method and apparatus for synchronising multiple serial datastreams in parallel
JP2001502137A (ja) 波形選択用位相誤差フィードバックを有する周波数合成器
EP1307960B1 (en) Frequency synthesizer
US7236552B2 (en) Data transmission
JP3507854B2 (ja) デジタルフェーズロックループ
US5050195A (en) Narrow range digital clock circuit
RU2119717C1 (ru) Устройство фазовой синхронизации
EP1020994A1 (en) PLL with variable (N+1/2) frequency dividing ratio
EP1005164A1 (en) Variable frequency divider
EP1385294A1 (en) Method and apparatus for phase-aligning two clock signals
GB2052815A (en) Digital frequency multiplier

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20111220

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20121230

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20121230

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301