JP3538994B2 - ディジタルカウンタおよびディジタルｐｌｌ回路 - Google Patents

ディジタルカウンタおよびディジタルｐｌｌ回路

Info

Publication number
JP3538994B2
JP3538994B2 JP24204495A JP24204495A JP3538994B2 JP 3538994 B2 JP3538994 B2 JP 3538994B2 JP 24204495 A JP24204495 A JP 24204495A JP 24204495 A JP24204495 A JP 24204495A JP 3538994 B2 JP3538994 B2 JP 3538994B2
Authority
JP
Japan
Prior art keywords
counter
significant bit
digital
count value
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24204495A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0993120A (ja
Inventor
弘 柳内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24204495A priority Critical patent/JP3538994B2/ja
Priority to KR1019960038662A priority patent/KR100414864B1/ko
Priority to TW085111194A priority patent/TW320796B/zh
Priority to US08/714,275 priority patent/US5896428A/en
Publication of JPH0993120A publication Critical patent/JPH0993120A/ja
Application granted granted Critical
Publication of JP3538994B2 publication Critical patent/JP3538994B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP24204495A 1995-09-20 1995-09-20 ディジタルカウンタおよびディジタルｐｌｌ回路 Expired - Fee Related JP3538994B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP24204495A JP3538994B2 (ja) 1995-09-20 1995-09-20 ディジタルカウンタおよびディジタルｐｌｌ回路
KR1019960038662A KR100414864B1 (ko) 1995-09-20 1996-09-06 디지탈카운터및디지탈pll회로
TW085111194A TW320796B (enExample) 1995-09-20 1996-09-13
US08/714,275 US5896428A (en) 1995-09-20 1996-09-17 Digital counter and digital phase locked loop circuit using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24204495A JP3538994B2 (ja) 1995-09-20 1995-09-20 ディジタルカウンタおよびディジタルｐｌｌ回路

Publications (2)

Publication Number Publication Date
JPH0993120A JPH0993120A (ja) 1997-04-04
JP3538994B2 true JP3538994B2 (ja) 2004-06-14

Family

ID=17083440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24204495A Expired - Fee Related JP3538994B2 (ja) 1995-09-20 1995-09-20 ディジタルカウンタおよびディジタルｐｌｌ回路

Country Status (4)

Country Link
US (1) US5896428A (enExample)
JP (1) JP3538994B2 (enExample)
KR (1) KR100414864B1 (enExample)
TW (1) TW320796B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049238A (en) * 1998-05-12 2000-04-11 Mitsubishi Denki Kabushiki Kaisha Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements
DE19850567C2 (de) * 1998-11-02 2001-02-15 Wandel & Goltermann Man Holdin Verwendung einer Schaltungsanordnung und Vorrichtung zur Messung der Signalgüte eines digitalen Nachrichtenübertragungssystems
US6760394B1 (en) * 1999-08-11 2004-07-06 Broadcom Corporation CMOS lock detect with double protection
US6708026B1 (en) * 2000-01-11 2004-03-16 Ericsson Inc. Division based local oscillator for frequency synthesis
KR100459854B1 (ko) * 2000-12-22 2004-12-03 엘지전자 주식회사 씨피유의 연산 처리 방법
GB0111300D0 (en) * 2001-05-09 2001-06-27 Mitel Knowledge Corp Method and apparatus for synchronizing slave network node to master network node
CN100349378C (zh) * 2002-04-19 2007-11-14 陈为怀 网同步可集成从时钟锁相环
US7151399B2 (en) * 2004-02-02 2006-12-19 Toshiba America Electronic Components, Inc. System and method for generating multiple clock signals
TWI274474B (en) * 2005-01-06 2007-02-21 Univ Nat Sun Yat Sen Phase-locked loop circuit and a method thereof
US20060187899A1 (en) * 2005-02-02 2006-08-24 Gemtek Systems, Inc. System of providing communication service via client representatives and the method of the same
US8369452B2 (en) * 2007-12-07 2013-02-05 Micron Technology, Inc. Majority detector apparatus, systems, and methods
KR101231743B1 (ko) * 2009-04-24 2013-02-08 한국전자통신연구원 디지털 락 검출장치 및 이를 포함하는 주파수 합성기
US8766689B2 (en) * 2010-12-29 2014-07-01 Telefonaktiebolaget L M Ericsson (Publ) Phase-frequency detection method
US10727847B1 (en) 2019-02-07 2020-07-28 International Business Machines Corporation Digital control of a voltage controlled oscillator frequency

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4272729A (en) * 1979-05-10 1981-06-09 Harris Corporation Automatic pretuning of a voltage controlled oscillator in a frequency synthesizer using successive approximation
JPH0744445B2 (ja) * 1983-05-31 1995-05-15 松下電器産業株式会社 デジタルｐｌｌ回路
JP3329088B2 (ja) * 1994-02-16 2002-09-30 株式会社デンソー パルス発生装置，周波数可変発振装置及びｐｌｌ装置
JP2771464B2 (ja) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5651036A (en) * 1996-05-09 1997-07-22 National Semiconductor Corporation Third harmonic suppression scheme for a wave used in a phase-to-frequency converter

Also Published As

Publication number Publication date
US5896428A (en) 1999-04-20
KR100414864B1 (ko) 2004-03-24
TW320796B (enExample) 1997-11-21
KR970019097A (ko) 1997-04-30
JPH0993120A (ja) 1997-04-04

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