KR100348233B1 - 반도체장치의제조방법 - Google Patents

반도체장치의제조방법 Download PDF

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Publication number
KR100348233B1
KR100348233B1 KR1019950012817A KR19950012817A KR100348233B1 KR 100348233 B1 KR100348233 B1 KR 100348233B1 KR 1019950012817 A KR1019950012817 A KR 1019950012817A KR 19950012817 A KR19950012817 A KR 19950012817A KR 100348233 B1 KR100348233 B1 KR 100348233B1
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South Korea
Prior art keywords
semiconductor
layer
slice
conductive
insulating layer
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Expired - Lifetime
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KR1019950012817A
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English (en)
Korean (ko)
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KR950034534A (ko
Inventor
로날드데커
헨리쿠스고데프리더스라파엘마스
빌헬르무스테오도러스안토니우스요하네스반덴아인덴
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코닌클리케 필립스 일렉트로닉스 엔.브이.
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Publication of KR950034534A publication Critical patent/KR950034534A/ko
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Publication of KR100348233B1 publication Critical patent/KR100348233B1/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/012Bonding, e.g. electrostatic for strain gauges

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Weting (AREA)
KR1019950012817A 1994-05-24 1995-05-23 반도체장치의제조방법 Expired - Lifetime KR100348233B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
BE09400527 1994-05-24
BE9400527A BE1008384A3 (nl) 1994-05-24 1994-05-24 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met halfgeleiderelementen gevormd in een op een dragerplak aangebrachte laag halfgeleidermateriaal.
BE941527 1994-05-24

Publications (2)

Publication Number Publication Date
KR950034534A KR950034534A (ko) 1995-12-28
KR100348233B1 true KR100348233B1 (ko) 2002-11-02

Family

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KR1019950012817A Expired - Lifetime KR100348233B1 (ko) 1994-05-24 1995-05-23 반도체장치의제조방법

Country Status (8)

Country Link
US (1) US5504036A (cg-RX-API-DMAC7.html)
EP (1) EP0684643B1 (cg-RX-API-DMAC7.html)
JP (1) JP2987081B2 (cg-RX-API-DMAC7.html)
KR (1) KR100348233B1 (cg-RX-API-DMAC7.html)
CN (1) CN1061783C (cg-RX-API-DMAC7.html)
BE (1) BE1008384A3 (cg-RX-API-DMAC7.html)
DE (1) DE69505048T2 (cg-RX-API-DMAC7.html)
TW (1) TW288193B (cg-RX-API-DMAC7.html)

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WO1998019337A1 (en) * 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
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US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US5897371A (en) * 1996-12-19 1999-04-27 Cypress Semiconductor Corp. Alignment process compatible with chemical mechanical polishing
EP1148546A1 (de) * 2000-04-19 2001-10-24 Infineon Technologies AG Verfahren zur Justierung von Strukturen auf einem Halbleiter-substrat
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
JP3788268B2 (ja) * 2001-05-14 2006-06-21 ソニー株式会社 半導体装置の製造方法
TW487958B (en) * 2001-06-07 2002-05-21 Ind Tech Res Inst Manufacturing method of thin film transistor panel
US7831151B2 (en) 2001-06-29 2010-11-09 John Trezza Redundant optical device array
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP4110390B2 (ja) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
US20030189215A1 (en) * 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
US8294172B2 (en) 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
US6841802B2 (en) * 2002-06-26 2005-01-11 Oriol, Inc. Thin film light emitting diode
JP2005150686A (ja) 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
US20080094725A1 (en) * 2004-08-09 2008-04-24 Koninklijke Philips Electronics, N.V. Method for bringing together at least two predetermined quantities of fluid and/or gas
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Publication number Publication date
BE1008384A3 (nl) 1996-04-02
EP0684643B1 (en) 1998-09-30
CN1115118A (zh) 1996-01-17
JP2987081B2 (ja) 1999-12-06
US5504036A (en) 1996-04-02
DE69505048T2 (de) 1999-05-12
CN1061783C (zh) 2001-02-07
JPH07321298A (ja) 1995-12-08
KR950034534A (ko) 1995-12-28
EP0684643A1 (en) 1995-11-29
TW288193B (cg-RX-API-DMAC7.html) 1996-10-11
DE69505048D1 (de) 1998-11-05

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