KR100263483B1 - 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 - Google Patents
고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 Download PDFInfo
- Publication number
- KR100263483B1 KR100263483B1 KR1019980017401A KR19980017401A KR100263483B1 KR 100263483 B1 KR100263483 B1 KR 100263483B1 KR 1019980017401 A KR1019980017401 A KR 1019980017401A KR 19980017401 A KR19980017401 A KR 19980017401A KR 100263483 B1 KR100263483 B1 KR 100263483B1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- delay
- phase
- measurement
- clock
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 12
- 238000005259 measurement Methods 0.000 claims abstract description 106
- 230000000630 rising effect Effects 0.000 claims abstract description 16
- 238000001514 detection method Methods 0.000 claims description 26
- 230000003111 delayed effect Effects 0.000 abstract description 8
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 abstract description 3
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 29
- 230000001360 synchronised effect Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000018199 S phase Effects 0.000 description 2
- 230000007334 memory performance Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980017401A KR100263483B1 (ko) | 1998-05-14 | 1998-05-14 | 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 |
| TW087120926A TW430804B (en) | 1998-05-14 | 1998-12-16 | Fast phase lock circuit and phase locking method thereof |
| JP11129673A JP3143743B2 (ja) | 1998-05-14 | 1999-05-11 | 高速位相同期回路及びこれを用いた位相同期方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980017401A KR100263483B1 (ko) | 1998-05-14 | 1998-05-14 | 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990085179A KR19990085179A (ko) | 1999-12-06 |
| KR100263483B1 true KR100263483B1 (ko) | 2000-08-01 |
Family
ID=19537345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980017401A KR100263483B1 (ko) | 1998-05-14 | 1998-05-14 | 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3143743B2 (ja) |
| KR (1) | KR100263483B1 (ja) |
| TW (1) | TW430804B (ja) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3807593B2 (ja) * | 2000-07-24 | 2006-08-09 | 株式会社ルネサステクノロジ | クロック生成回路および制御方法並びに半導体記憶装置 |
| KR100446291B1 (ko) * | 2001-11-07 | 2004-09-01 | 삼성전자주식회사 | 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로 |
| JP4642417B2 (ja) * | 2004-09-16 | 2011-03-02 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| JP4850473B2 (ja) | 2005-10-13 | 2012-01-11 | 富士通セミコンダクター株式会社 | デジタル位相検出器 |
| KR100728907B1 (ko) | 2006-06-26 | 2007-06-15 | 주식회사 하이닉스반도체 | 반도체 메모리의 클럭신호 생성장치 및 방법 |
-
1998
- 1998-05-14 KR KR1019980017401A patent/KR100263483B1/ko not_active IP Right Cessation
- 1998-12-16 TW TW087120926A patent/TW430804B/zh not_active IP Right Cessation
-
1999
- 1999-05-11 JP JP11129673A patent/JP3143743B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW430804B (en) | 2001-04-21 |
| JP2000029564A (ja) | 2000-01-28 |
| KR19990085179A (ko) | 1999-12-06 |
| JP3143743B2 (ja) | 2001-03-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080425 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |