TW430804B - Fast phase lock circuit and phase locking method thereof - Google Patents

Fast phase lock circuit and phase locking method thereof

Info

Publication number
TW430804B
TW430804B TW087120926A TW87120926A TW430804B TW 430804 B TW430804 B TW 430804B TW 087120926 A TW087120926 A TW 087120926A TW 87120926 A TW87120926 A TW 87120926A TW 430804 B TW430804 B TW 430804B
Authority
TW
Taiwan
Prior art keywords
delay
signal
measure
phase
input signal
Prior art date
Application number
TW087120926A
Other languages
English (en)
Inventor
Buu-Young Park
Original Assignee
Lg Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Semicon Co Ltd filed Critical Lg Semicon Co Ltd
Application granted granted Critical
Publication of TW430804B publication Critical patent/TW430804B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
TW087120926A 1998-05-14 1998-12-16 Fast phase lock circuit and phase locking method thereof TW430804B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980017401A KR100263483B1 (ko) 1998-05-14 1998-05-14 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법

Publications (1)

Publication Number Publication Date
TW430804B true TW430804B (en) 2001-04-21

Family

ID=19537345

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087120926A TW430804B (en) 1998-05-14 1998-12-16 Fast phase lock circuit and phase locking method thereof

Country Status (3)

Country Link
JP (1) JP3143743B2 (zh)
KR (1) KR100263483B1 (zh)
TW (1) TW430804B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3807593B2 (ja) * 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
JP4642417B2 (ja) * 2004-09-16 2011-03-02 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP4850473B2 (ja) 2005-10-13 2012-01-11 富士通セミコンダクター株式会社 デジタル位相検出器
KR100728907B1 (ko) * 2006-06-26 2007-06-15 주식회사 하이닉스반도체 반도체 메모리의 클럭신호 생성장치 및 방법

Also Published As

Publication number Publication date
JP2000029564A (ja) 2000-01-28
KR19990085179A (ko) 1999-12-06
KR100263483B1 (ko) 2000-08-01
JP3143743B2 (ja) 2001-03-07

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees