DE69936064D1 - Jitterarmes pll-taktrückgewinnungssystem hoher phasenauflösung - Google Patents

Jitterarmes pll-taktrückgewinnungssystem hoher phasenauflösung

Info

Publication number
DE69936064D1
DE69936064D1 DE69936064T DE69936064T DE69936064D1 DE 69936064 D1 DE69936064 D1 DE 69936064D1 DE 69936064 T DE69936064 T DE 69936064T DE 69936064 T DE69936064 T DE 69936064T DE 69936064 D1 DE69936064 D1 DE 69936064D1
Authority
DE
Germany
Prior art keywords
phase
vco
output
phase resolution
clock frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69936064T
Other languages
English (en)
Other versions
DE69936064T2 (de
Inventor
Myles Wakayama
Stephen A Jantzi
Kwang Young Kim
Yee Ling Cheung
Ka Wai Tong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE69936064D1 publication Critical patent/DE69936064D1/de
Publication of DE69936064T2 publication Critical patent/DE69936064T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
DE69936064T 1998-12-07 1999-12-07 Jitterarmes pll-taktrückgewinnungssystem hoher phasenauflösung Expired - Lifetime DE69936064T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11055798P 1998-12-07 1998-12-07
US110557P 1998-12-07
PCT/US1999/029083 WO2000035094A1 (en) 1998-12-07 1999-12-07 Low jitter high phase resolution pll-based timing recovery system

Publications (2)

Publication Number Publication Date
DE69936064D1 true DE69936064D1 (de) 2007-06-21
DE69936064T2 DE69936064T2 (de) 2008-01-10

Family

ID=22333669

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69936064T Expired - Lifetime DE69936064T2 (de) 1998-12-07 1999-12-07 Jitterarmes pll-taktrückgewinnungssystem hoher phasenauflösung

Country Status (5)

Country Link
EP (1) EP1145440B1 (de)
AT (1) ATE362227T1 (de)
AU (1) AU3114400A (de)
DE (1) DE69936064T2 (de)
WO (1) WO2000035094A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934387B1 (en) 1999-12-17 2005-08-23 Marvell International Ltd. Method and apparatus for digital near-end echo/near-end crosstalk cancellation with adaptive correlation
US6816505B1 (en) 2000-02-09 2004-11-09 Marvell International Ltd. Chip-to-chip interface for 1000 BASE T gigabit physical layer device
USRE41831E1 (en) 2000-05-23 2010-10-19 Marvell International Ltd. Class B driver
US6775529B1 (en) 2000-07-31 2004-08-10 Marvell International Ltd. Active resistive summer for a transformer hybrid
US6577114B1 (en) 2000-07-31 2003-06-10 Marvell International, Ltd. Calibration circuit
US7606547B1 (en) 2000-07-31 2009-10-20 Marvell International Ltd. Active resistance summer for a transformer hybrid
US7570657B1 (en) 2000-12-15 2009-08-04 Marvell International Ltd. Autonegotiation between 1000Base-X and 1000Base-T

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068628A (en) * 1990-11-13 1991-11-26 Level One Communications, Inc. Digitally controlled timing recovery loop
US5126691A (en) * 1991-06-17 1992-06-30 Motorola, Inc. Variable clock delay circuit
US5268656A (en) * 1992-11-05 1993-12-07 At&T Bell Laboratories Programmable clock skew adjustment circuit
US5493243A (en) * 1994-01-04 1996-02-20 Level One Communications, Inc. Digitally controlled first order jitter attentuator using a digital frequency synthesizer

Also Published As

Publication number Publication date
WO2000035094A1 (en) 2000-06-15
DE69936064T2 (de) 2008-01-10
ATE362227T1 (de) 2007-06-15
EP1145440B1 (de) 2007-05-09
EP1145440A1 (de) 2001-10-17
AU3114400A (en) 2000-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M