KR100193103B1 - 반도체집적회로장치 및 리프레시타이머 주기조정방법 - Google Patents

반도체집적회로장치 및 리프레시타이머 주기조정방법 Download PDF

Info

Publication number
KR100193103B1
KR100193103B1 KR1019960002946A KR19960002946A KR100193103B1 KR 100193103 B1 KR100193103 B1 KR 100193103B1 KR 1019960002946 A KR1019960002946 A KR 1019960002946A KR 19960002946 A KR19960002946 A KR 19960002946A KR 100193103 B1 KR100193103 B1 KR 100193103B1
Authority
KR
South Korea
Prior art keywords
memory cell
electrode
refresh
potential
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960002946A
Other languages
English (en)
Korean (ko)
Other versions
KR960032486A (ko
Inventor
히로유키 야마우치
도오루 이와타
Original Assignee
무명씨
마츠시타 덴끼 산교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 무명씨, 마츠시타 덴끼 산교 가부시키가이샤 filed Critical 무명씨
Publication of KR960032486A publication Critical patent/KR960032486A/ko
Application granted granted Critical
Publication of KR100193103B1 publication Critical patent/KR100193103B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4068—Voltage or leakage in refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1019960002946A 1995-02-08 1996-02-07 반도체집적회로장치 및 리프레시타이머 주기조정방법 Expired - Fee Related KR100193103B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2054595 1995-02-08
JP95-020,545 1995-02-08

Publications (2)

Publication Number Publication Date
KR960032486A KR960032486A (ko) 1996-09-17
KR100193103B1 true KR100193103B1 (ko) 1999-06-15

Family

ID=12030132

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960002946A Expired - Fee Related KR100193103B1 (ko) 1995-02-08 1996-02-07 반도체집적회로장치 및 리프레시타이머 주기조정방법

Country Status (3)

Country Link
US (1) US5652729A (enExample)
KR (1) KR100193103B1 (enExample)
TW (1) TW301750B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744598B1 (ko) * 2001-06-29 2007-08-01 매그나칩 반도체 유한회사 리프레쉬 회로 및 방법 및 이를 이용하는 반도체 메모리장치
US7835198B2 (en) 2007-03-05 2010-11-16 Hynix Semiconductor Inc. Apparatus and method for detecting leakage current of semiconductor memory device, and internal voltage generating circuit using the same

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784328A (en) * 1996-12-23 1998-07-21 Lsi Logic Corporation Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
JPH10199293A (ja) * 1996-12-27 1998-07-31 Canon Inc メモリのデータ保持特性の試験方法
US5956350A (en) * 1997-10-27 1999-09-21 Lsi Logic Corporation Built in self repair for DRAMs using on-chip temperature sensing and heating
FR2775382B1 (fr) * 1998-02-25 2001-10-05 St Microelectronics Sa Procede de controle du rafraichissement d'un plan memoire d'un dispositif de memoire vive dynamique, et dispositif de memoire vive correspondant
US5909404A (en) * 1998-03-27 1999-06-01 Lsi Logic Corporation Refresh sampling built-in self test and repair circuit
US6504780B2 (en) 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6898140B2 (en) * 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
KR100641912B1 (ko) * 1998-12-24 2007-07-12 주식회사 하이닉스반도체 셀 누설전류 감지장치
US6115310A (en) * 1999-01-05 2000-09-05 International Business Machines Corporation Wordline activation delay monitor using sample wordline located in data-storing array
US6185135B1 (en) 1999-01-05 2001-02-06 International Business Machines Corporation Robust wordline activation delay monitor using a plurality of sample wordlines
DE10002374C2 (de) 2000-01-20 2002-10-17 Infineon Technologies Ag Halbleiter-Speicheranordnung mit Auffrischungslogikschaltung sowie Verfahren zum Auffrischen des Speicherinhaltes einer Halbleiter-Speicheranordnung
US6269039B1 (en) 2000-04-04 2001-07-31 International Business Machines Corp. System and method for refreshing memory devices
EP1324491A4 (en) * 2000-08-04 2008-05-14 Nec Electronics Corp TIMER SWITCHING AND SEMICONDUCTOR MEMORY WITH TEMPERATURE SWITCHING
US6483764B2 (en) * 2001-01-16 2002-11-19 International Business Machines Corporation Dynamic DRAM refresh rate adjustment based on cell leakage monitoring
JP2003030983A (ja) * 2001-07-13 2003-01-31 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
JP4392740B2 (ja) * 2001-08-30 2010-01-06 株式会社ルネサステクノロジ 半導体記憶回路
US6714473B1 (en) 2001-11-30 2004-03-30 Cypress Semiconductor Corp. Method and architecture for refreshing a 1T memory proportional to temperature
US6791893B2 (en) * 2002-06-12 2004-09-14 Micron Technology, Inc. Regulating voltages in semiconductor devices
TWI285894B (en) * 2003-04-17 2007-08-21 Winbond Electronics Corp Generation device of the refresh clock varied with the capacitance of memory capacitor and method thereof
JP4199591B2 (ja) * 2003-05-16 2008-12-17 エルピーダメモリ株式会社 セルリークモニタ回路及びモニタ方法
US20050036380A1 (en) * 2003-08-14 2005-02-17 Yuan-Mou Su Method and system of adjusting DRAM refresh interval
US7225375B2 (en) * 2004-03-31 2007-05-29 International Business Machines Corporation Method and apparatus for detecting array degradation and logic degradation
JP2005332446A (ja) * 2004-05-18 2005-12-02 Fujitsu Ltd 半導体メモリ
JP4783027B2 (ja) * 2005-01-24 2011-09-28 パナソニック株式会社 半導体記憶装置
US7564274B2 (en) * 2005-02-24 2009-07-21 Icera, Inc. Detecting excess current leakage of a CMOS device
US7274618B2 (en) 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
KR100712528B1 (ko) * 2005-08-26 2007-04-27 삼성전자주식회사 센싱마진 가변회로 및 이를 구비하는 반도체 메모리 장치
US7882334B2 (en) * 2006-02-20 2011-02-01 International Business Machines Corporation Processor pipeline architecture logic state retention systems and methods
US7397718B2 (en) * 2006-04-13 2008-07-08 International Business Machines Corporation Determining relative amount of usage of data retaining device based on potential of charge storing device
KR100800145B1 (ko) * 2006-05-22 2008-02-01 주식회사 하이닉스반도체 셀프 리프레쉬 주기 제어 회로 및 그 방법
JP4882007B2 (ja) * 2007-01-05 2012-02-22 プロトン ワールド インターナショナル エヌ．ヴィ． 電子回路の一時的なロック
JP5070297B2 (ja) * 2007-01-05 2012-11-07 プロトン ワールド インターナショナル エヌ．ヴィ． 電子回路に含まれる情報の保護
JP2008293605A (ja) * 2007-05-25 2008-12-04 Elpida Memory Inc 半導体記憶装置
US7913193B2 (en) * 2007-10-26 2011-03-22 International Business Machines Corporation Determining relative amount of usage of data retaining device based on potential of charge storing device
US7937560B2 (en) * 2008-05-15 2011-05-03 International Business Machines Corporation Processor pipeline architecture logic state retention systems and methods
KR20130098473A (ko) * 2012-02-28 2013-09-05 삼성전자주식회사 테스트 핸들러의 챔버 내부온도 측정방법 및 온도 실시간 조정방법
KR101982194B1 (ko) 2012-06-20 2019-05-24 에스케이하이닉스 주식회사 지연 제어회로 및 이를 포함하는 클럭 생성회로
KR20150138026A (ko) * 2014-05-29 2015-12-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6084318B1 (ja) * 2016-02-22 2017-02-22 力晶科技股▲ふん▼有限公司 揮発性半導体記憶装置のリフレッシュ制御回路及び方法、並びに揮発性半導体記憶装置
US10482981B2 (en) * 2018-02-20 2019-11-19 Sandisk Technologies Llc Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors
USD943943S1 (en) 2020-07-24 2022-02-22 New Balance Athletics, Inc. Shoe upper
US11195568B1 (en) 2020-08-12 2021-12-07 Samsung Electronics Co., Ltd. Methods and systems for controlling refresh operations of a memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787034B2 (ja) * 1984-05-07 1995-09-20 株式会社日立製作所 半導体集積回路装置
JPH07107793B2 (ja) * 1987-11-10 1995-11-15 株式会社東芝 仮想型スタティック半導体記憶装置及びこの記憶装置を用いたシステム
JPH04259983A (ja) * 1991-02-15 1992-09-16 Hitachi Ltd 半導体記憶装置
KR920022293A (ko) * 1991-05-16 1992-12-19 김광호 비정기적인 리프레쉬 동작을 실행하는 반도체 메모리 장치
JPH05225777A (ja) * 1992-02-13 1993-09-03 Sharp Corp 半導体メモリ装置
US5392251A (en) * 1993-07-13 1995-02-21 Micron Semiconductor, Inc. Controlling dynamic memory refresh cycle time

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744598B1 (ko) * 2001-06-29 2007-08-01 매그나칩 반도체 유한회사 리프레쉬 회로 및 방법 및 이를 이용하는 반도체 메모리장치
US7835198B2 (en) 2007-03-05 2010-11-16 Hynix Semiconductor Inc. Apparatus and method for detecting leakage current of semiconductor memory device, and internal voltage generating circuit using the same

Also Published As

Publication number Publication date
TW301750B (enExample) 1997-04-01
US5652729A (en) 1997-07-29
KR960032486A (ko) 1996-09-17

Similar Documents

Publication Publication Date Title
KR100193103B1 (ko) 반도체집적회로장치 및 리프레시타이머 주기조정방법
US5963103A (en) Temperature sensitive oscillator circuit
US5680359A (en) Self-refresh period adjustment circuit for semiconductor memory device
US5774404A (en) Semiconductor memory having self-refresh function
US6426671B1 (en) Internal voltage generating circuit
US6483764B2 (en) Dynamic DRAM refresh rate adjustment based on cell leakage monitoring
CN100433185C (zh) 自刷新振荡器
US6731558B2 (en) Semiconductor device
US6054885A (en) Semiconductor device and testing apparatus thereof
US20030189869A1 (en) Semiconductor integrated circuit device having hierarchical power source arrangement
EP0602355B1 (en) Fuse programmable voltage down converter
US5453959A (en) Semiconductor memory device having a self-refreshing control circuit
EP0176203B1 (en) Self refresh control circuit for dynamic semiconductor memory device
JPH07141865A (ja) 発振回路および半導体記憶装置
US6992942B2 (en) Cell leakage monitoring circuit and monitoring method
US20050052923A1 (en) Semiconductor apparatus capable of performing refresh control
US7292489B2 (en) Circuits and methods of temperature compensation for refresh oscillator
US11342906B2 (en) Delay circuits, and related semiconductor devices and methods
US9171599B2 (en) Circuits, apparatuses, and methods for oscillators
JP3029396B2 (ja) 半導体集積回路装置及びリフレッシュタイマー周期調整方法
KR20060118733A (ko) 반도체 장치의 온도 보상 발진 회로
US20130315009A1 (en) Period signal generation circuit
US8923080B2 (en) Period signal generation circuit
US9070476B2 (en) Refresh circuits
US8811099B2 (en) Period signal generation circuits

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

G170 Re-publication after modification of scope of protection [patent]
PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

FPAY Annual fee payment

Payment date: 20110126

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20120203

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20120203

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301