KR0165856B1 - 침착 터널링 산화물의 제조방법 - Google Patents

침착 터널링 산화물의 제조방법 Download PDF

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Publication number
KR0165856B1
KR0165856B1 KR1019900700109A KR900700109A KR0165856B1 KR 0165856 B1 KR0165856 B1 KR 0165856B1 KR 1019900700109 A KR1019900700109 A KR 1019900700109A KR 900700109 A KR900700109 A KR 900700109A KR 0165856 B1 KR0165856 B1 KR 0165856B1
Authority
KR
South Korea
Prior art keywords
layer
tunneling
silicon dioxide
dioxide layer
forming
Prior art date
Application number
KR1019900700109A
Other languages
English (en)
Korean (ko)
Other versions
KR900702567A (ko
Inventor
스티븐 바스케 그레고리
Original Assignee
윌리엄 에이취 오우웬
자이코오 인코포레이팃드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리엄 에이취 오우웬, 자이코오 인코포레이팃드 filed Critical 윌리엄 에이취 오우웬
Publication of KR900702567A publication Critical patent/KR900702567A/ko
Application granted granted Critical
Publication of KR0165856B1 publication Critical patent/KR0165856B1/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
KR1019900700109A 1988-05-17 1989-05-16 침착 터널링 산화물의 제조방법 KR0165856B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19576688A 1988-05-17 1988-05-17
US195,766 1988-05-17
PCT/US1989/002111 WO1989011731A1 (fr) 1988-05-17 1989-05-16 Depot d'oxyde a effet tunnel

Publications (2)

Publication Number Publication Date
KR900702567A KR900702567A (ko) 1990-12-07
KR0165856B1 true KR0165856B1 (ko) 1999-02-01

Family

ID=22722714

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900700109A KR0165856B1 (ko) 1988-05-17 1989-05-16 침착 터널링 산화물의 제조방법

Country Status (4)

Country Link
EP (1) EP0417197A4 (fr)
JP (1) JP2703638B2 (fr)
KR (1) KR0165856B1 (fr)
WO (1) WO1989011731A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101713B2 (ja) * 1988-06-07 1995-11-01 三菱電機株式会社 半導体記憶装置の製造方法
US5153691A (en) * 1989-06-21 1992-10-06 Xicor, Inc. Apparatus for a dual thickness floating gate memory cell
US5593494A (en) * 1995-03-14 1997-01-14 Memc Electronic Materials, Inc. Precision controlled precipitation of oxygen in silicon
JP3245136B2 (ja) * 1999-09-01 2002-01-07 キヤノン販売株式会社 絶縁膜の膜質改善方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3934060A (en) * 1973-12-19 1976-01-20 Motorola, Inc. Method for forming a deposited silicon dioxide layer on a semiconductor wafer
US4613956A (en) * 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric
JPS60148168A (ja) * 1984-01-13 1985-08-05 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
US4713677A (en) * 1985-02-28 1987-12-15 Texas Instruments Incorporated Electrically erasable programmable read only memory cell including trench capacitor
US4599706A (en) * 1985-05-14 1986-07-08 Xicor, Inc. Nonvolatile electrically alterable memory

Also Published As

Publication number Publication date
JPH03505145A (ja) 1991-11-07
EP0417197A1 (fr) 1991-03-20
KR900702567A (ko) 1990-12-07
JP2703638B2 (ja) 1998-01-26
WO1989011731A1 (fr) 1989-11-30
EP0417197A4 (en) 1992-07-08

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