EP0417197A1 - Depot d'oxyde a effet tunnel - Google Patents

Depot d'oxyde a effet tunnel

Info

Publication number
EP0417197A1
EP0417197A1 EP89907002A EP89907002A EP0417197A1 EP 0417197 A1 EP0417197 A1 EP 0417197A1 EP 89907002 A EP89907002 A EP 89907002A EP 89907002 A EP89907002 A EP 89907002A EP 0417197 A1 EP0417197 A1 EP 0417197A1
Authority
EP
European Patent Office
Prior art keywords
layer
silicon dioxide
polysilicon
oxide
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP89907002A
Other languages
German (de)
English (en)
Other versions
EP0417197A4 (en
Inventor
Gregory Steven Vasche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xicor LLC
Original Assignee
Xicor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xicor LLC filed Critical Xicor LLC
Publication of EP0417197A1 publication Critical patent/EP0417197A1/fr
Publication of EP0417197A4 publication Critical patent/EP0417197A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Definitions

  • This invention relates to the field of integrated circuit processing and more specifically to a method of depositing tunneling oxide in an electrically eraseable read-only memory device.
  • EEPROM devices are nonvolatile memory devices in which the presence or absence of charge on a floating gate electrode indicates a binary one or zero.
  • One EEPROM device is described in United States Patent No. 4,579,706, entitled “Nonvolatile Electrically Alterable Memory”. This patent is herein incorporated by reference.
  • the floating gate electrode is electrically insulated from the other electrodes of the device by one or more layers of tunneling oxide. Electrical charge is transferred to the floating gate by placing a voltage on a programming electrode which is sufficient to cause electrons to tunnel through the tunneling oxide to the floating gate electrode.
  • the tunneling oxide can conduct only a limited amount of charge under the high fields imposed across the oxide during tunneling before the tunneling oxide fails or breaks down, thus limiting the number of programming cycles. In some tunneling elements in an EEPROM array, this failure may occur in less than approximately 10,000 programming cycles, depending on the uniformity and intrinsic defect density of the tunneling oxide layer ot layers.
  • tunneling oxide layer The characteristics of the tunneling oxide layer are critical to the life and operation of an EEPROM device.
  • tunneling oxides are produced by growing an oxide using a thermal oxidation process.
  • the oxide defect density is quite high, which causes a large number of early breakdown failures. As presently understood, this is because any defects in the underlying silicon may propagate into the silicon dioxide layer as it is grown.
  • the tunneling oxide develops a high level of stress. As presently understood, -this phenomena causes defects resulting in early or premature failures in the oxide during tunneling, thus further limiting the life of the device.
  • No technique is known for thermally growing a low-stress tunneling oxide, while providing an oxide layer with substantially zero defects.
  • the present invention contemplates a method and means of depositing a tunneling oxide layer between two conductors with a low pressure, low temperature chemical vapor deposition (LPCVD) process.
  • LPCVD low pressure, low temperature chemical vapor deposition
  • TEOS tetraethylorthosilicate
  • the present method is used in an EEPROM device and polysilicon layers are used for forming the device, the deposited oxide i ⁇ formed as follows.
  • a first layer of polysilicon is deposited and patterned as desired.
  • the oxide layer formed from the deposited tetraethylorthosilicate is then thermally annealed and densified.
  • this i ⁇ performed using a mixture of steam and an inert gas, such as argon, at a predetermined temperature.
  • the process may be repeated where more than one tunneling layer is desired.
  • a layer of relatively thin oxide thermal oxide may be grown on the surface of the polysilicon.
  • Figure 1 is a cutaway view of a three layer thick-oxide EEPROM device constructed in accordance with the present invention.
  • Figures 2 is a flow diagram detailing a process for manufacturing one of the tunneling oxide 0 regions of the device of Figure 1. Detailed Description of the Invention
  • FIG. 1 there i ⁇ shown a cutaway view of a three layer polysilicon device which may advantageously employ the tunneling oxide layer of ⁇ the present invention.
  • the operation and manufacture of the device of Figure 1 is substantially described in U.S. Patent No. 4,599,706, the difference being the substitution of the present deposited oxide for the thermal oxide described in the above U.S. patent.
  • the EEPROM device 10 of Figure 1 is formed on a substrate 12 which comprises a "p"-type semiconductor material. Two n+ regions 20, 22 are diffused on opposing ends of the substrate. An n- region 24 is diffused in a central upper region of substrate 12. The n+ source, drain regions 20, 22 and n- diffusion 24 may be formed using a conventional well known ⁇ iffusion process.
  • the EEPROM device 10 further includes a polysilicon electrode 24 which i ⁇ i ⁇ olated from substrate 12 by oxide region 30 and polysilicon electrodes 26 and 28 which are separated from the substrate, and each other by tunneling oxide regions or elements 32 and 34.
  • the oxide used for forming these tunneling elements 32, 34 was thermally grown, which i ⁇ believed to cause stre ⁇ s and defects in tunneling oxide elements 32, 34 because defects from the underlying silicon substitute or pclysilicon region may propagate into the tunneling oxide.
  • the present invention contemplates the use of a low pressure chemical vapor deposition process to form elements 32, 34.
  • a thermal oxidation process once the tunneling oxides are grown, subsequent thermal proces ⁇ ing causes thermal stress in the oxide, thus causing additional breakdown and charge trap-up problems in the device.
  • the present invention contemplates the use of a low temperature process to minimize thermal oxide growth during the processing of the device, which significantly reduces stre ⁇ and thereby increases the useful life of the device. This feature has also been found to enhance electron tunneling in the resulting device.
  • the low pressure chemical vapor deposition process used according to the present invention for forming an oxide layer is believed to avoid the propagation of defects into the oxide from the underlying substrate or polysilicon.
  • Atmospheric deposition of silicon has been attempted in the pa ⁇ t using silicon rich Si ⁇ 2 in a chemical vapor deposition process.
  • One such process is described in an article entitled "Silicon - Rich Si ⁇ 2 and Thermal Si ⁇ 2 Dual Dielectric for Yield Improvement and High Capacitance", IEEE Transactions on Electron evice ⁇ , Vol. ED-30, No. 8, P. 894, August 1983.
  • the process described in this publication is experimental and has been found to be inadequate for use in rr.anufacturing tunneling oxides because silicon rich Si ⁇ 2 i ⁇ not a stoichiometric compound and thus contains impurities which affect the uniformity of the deposited cxide.
  • the u ⁇ e of an atmospheric deposition also creates large variations in thickness of the resulting layer and, therefore, silicon rich Si ⁇ 2 has only been used for relatively thick layers.
  • silicon rich Si ⁇ 2 has only been used for relatively thick layers.
  • the added silicon in the above proces ⁇ provides a form of enhancement for electron tunneling through the dielectric formed by this process, it's not as efficient a ⁇ the formation of a textured surface on the underlying silicon substrate or polysilicon conductive layer.
  • the silicon rich Si ⁇ 2 apparently forms regions or balls of silicon in the silicon dioxide near the surface therof but spread out. Thus, they are not conductive with each other or with the surface of the dielectric and so are less efficient a ⁇ enhanced emis ⁇ ion structures as compared with the textured surface of a polysilicon layer.
  • TEOS tetraethyl ⁇ orthosilicate
  • the present invention overcomes the above problem by modifying the known deposited oxide process using a den ⁇ ification or annealing step on the TEOS deposited oxide during processing. It has been found that by exposing the TEOS deposited oxide to a steam and inert gas mixture at a relatively high temperature, the properties of the TEOS oxide are modified to equal or exceed those of thermally grown oxides. The resulting material has substantially improved dielectric properties and the resulting material is substantially free of leakage and does not break down in the presence of a strong electric field. It is believed that this annealing process provides more uniform molecular bonding by permitting greater viscous flow in the TEOS deposited oxide thus reducing or eliminating defects in the resulting dielectric layer.
  • the inert gas provides a partial pressure which is used to slow this undesired oxide growth rate while allowing the annealing process to proceed.
  • the process of the present invention has been found to increase the total charge conducted through the dielectric layer by at least one order of magnitude before catastrophic breakdown, while at the same time providing a dramatic improvement in processing yields.
  • the process 200 begins with step 202 wherein an initial layer of gate oxide, approximately 400 Angstroms thick is deposited on a substrate.
  • This oxide layer may be formed with a conventional thermal oxide process.
  • the first layer of polysilicon is formed with a conventional polysilicon deposition process.
  • the first layer of polysilicon is deposited approximately 4000 Ang ⁇ tron ⁇ thick.
  • the first layer of polysilicon is doped to render the polysilicon layer conductive. Tne first layer of polysilicon may then be masked in step 210 and etched in step 212 using either a reactive ior. etcn or wet etch process.
  • each tunneling region be somewhat irregular to promote electron tunneling.
  • These surface irregularities or microtextured surfaces are formed by thermally oxidizing the surface of the polysilicon layer with step 216.
  • the thermal oxide of step 216 i ⁇ then etched back to leave a layer of oxide approximately 150 Angstroms thick.
  • the tunneling oxide layer is then formed by steps 220, 222 and 223.
  • the TEOS gas is supplied via a bubbler by direct pull with the furnace temperature at approximately 600°C.
  • the deposition rate is controlled primarily by the bubbler and furnace temperatures.
  • the oxide is deposited to create an oxide layer of between 250 and 2000 Angstroms thick.
  • This oxide layer is then annealed in steps 222 and 223.
  • the annealing process of step 222 is done by exposing the TEOS produced silicon dioxide layer to a gaseous mixture of steam and argon at a temperature range of approximately 700-1100°C for approximately 1-5 minutes. This is preferrably followed by further thermal annealing in a solely nitrogen ambient at step 223 to prevent further oxidation of the surface. This is performed at the same approximate temperature range for between 2 and 20 minutes.
  • Other annealing processes, such as rapid optical annealing may also be employed at different temperatures and timing a ⁇ is known in the art for thick deposited oxide layers.
  • step 224 the next layer of polysilicon, approximately 4000-6000 Angstroms thick, is deposited by conventional means.
  • the second layer of polysilicon is then doped in step 226.
  • the second layer of polysilicon is then masked for further processing in step 230.
  • decision 232 either route ⁇ the process back to step 212 or exits the process at step 234.
  • the resulting structure may then be metalized and finished according to conventional means.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un dispositif semiconducteur ainsi qu'un procédé pour déposer une couche d'oxyde à effet tunnel entre deux couches conductrices fondé sur un procédé de dépôt de vapeur chimique à basse température et basse pression (LPCVD) dans lequel on utilise de préférence du tétraéthylarthosilicate (TEOS). Comme il est appliqué à un dispositif à mémoire morte programmable électriquement effaçable (EEPROM) comportant des couches de polysilicium, on fabrique ledit dispositif en formant une première couche de polysilicium (24) configuré comme on le désire. Une couche de dioxyde de silicium est ensuite déposée par décomposition de TEOS pour former une épaisseur prédéterminée (32) d'oxyde à effet tunnel. Si l'on veut obtenir des structures à émission améliorée, on peut obtenir une couche d'oxyde à effet tunnel relativement mince sur la première couche de polysilicium. On procède ensuite au recuit et à la densification de la couche d'oxyde, de préférence à l'aide de vapeur et d'un gaz inerte à une température spécifique. On forme ensuite une seconde couche de polysilicium sur la couche d'oxide à effet tunnel (26).
EP19890907002 1988-05-17 1989-05-16 Deposited tunneling oxide Ceased EP0417197A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19576688A 1988-05-17 1988-05-17
US195766 1988-05-17

Publications (2)

Publication Number Publication Date
EP0417197A1 true EP0417197A1 (fr) 1991-03-20
EP0417197A4 EP0417197A4 (en) 1992-07-08

Family

ID=22722714

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890907002 Ceased EP0417197A4 (en) 1988-05-17 1989-05-16 Deposited tunneling oxide

Country Status (4)

Country Link
EP (1) EP0417197A4 (fr)
JP (1) JP2703638B2 (fr)
KR (1) KR0165856B1 (fr)
WO (1) WO1989011731A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101713B2 (ja) * 1988-06-07 1995-11-01 三菱電機株式会社 半導体記憶装置の製造方法
US5153691A (en) * 1989-06-21 1992-10-06 Xicor, Inc. Apparatus for a dual thickness floating gate memory cell
US5593494A (en) * 1995-03-14 1997-01-14 Memc Electronic Materials, Inc. Precision controlled precipitation of oxygen in silicon
JP3245136B2 (ja) * 1999-09-01 2002-01-07 キヤノン販売株式会社 絶縁膜の膜質改善方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613956A (en) * 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3934060A (en) * 1973-12-19 1976-01-20 Motorola, Inc. Method for forming a deposited silicon dioxide layer on a semiconductor wafer
JPS60148168A (ja) * 1984-01-13 1985-08-05 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
US4713677A (en) * 1985-02-28 1987-12-15 Texas Instruments Incorporated Electrically erasable programmable read only memory cell including trench capacitor
US4599706A (en) * 1985-05-14 1986-07-08 Xicor, Inc. Nonvolatile electrically alterable memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613956A (en) * 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B. vol. 5, no. 6, November 1987, NEW YORK US pages 1555 - 1563; F.S. BECKER ET AL.: 'Low-pressure deposition of high-quality SiO2 films by pyrolysis of tetraethylorthosilicate.' *
See also references of WO8911731A1 *

Also Published As

Publication number Publication date
JPH03505145A (ja) 1991-11-07
JP2703638B2 (ja) 1998-01-26
EP0417197A4 (en) 1992-07-08
KR900702567A (ko) 1990-12-07
KR0165856B1 (ko) 1999-02-01
WO1989011731A1 (fr) 1989-11-30

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