JPWO2021125138A5 - - Google Patents

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Publication number
JPWO2021125138A5
JPWO2021125138A5 JP2021565573A JP2021565573A JPWO2021125138A5 JP WO2021125138 A5 JPWO2021125138 A5 JP WO2021125138A5 JP 2021565573 A JP2021565573 A JP 2021565573A JP 2021565573 A JP2021565573 A JP 2021565573A JP WO2021125138 A5 JPWO2021125138 A5 JP WO2021125138A5
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JP
Japan
Prior art keywords
nanosheet
semiconductor memory
memory device
power supply
ground power
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JP2021565573A
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English (en)
Japanese (ja)
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JPWO2021125138A1 (https=
JP7610131B2 (ja
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Priority claimed from PCT/JP2020/046574 external-priority patent/WO2021125138A1/ja
Publication of JPWO2021125138A1 publication Critical patent/JPWO2021125138A1/ja
Publication of JPWO2021125138A5 publication Critical patent/JPWO2021125138A5/ja
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Publication of JP7610131B2 publication Critical patent/JP7610131B2/ja
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JP2021565573A 2019-12-20 2020-12-14 半導体記憶装置 Active JP7610131B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019230713 2019-12-20
JP2019230713 2019-12-20
PCT/JP2020/046574 WO2021125138A1 (ja) 2019-12-20 2020-12-14 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPWO2021125138A1 JPWO2021125138A1 (https=) 2021-06-24
JPWO2021125138A5 true JPWO2021125138A5 (https=) 2022-08-15
JP7610131B2 JP7610131B2 (ja) 2025-01-08

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Family Applications (1)

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JP2021565573A Active JP7610131B2 (ja) 2019-12-20 2020-12-14 半導体記憶装置

Country Status (4)

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US (1) US12279419B2 (https=)
JP (1) JP7610131B2 (https=)
CN (1) CN114868242B (https=)
WO (1) WO2021125138A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7640861B2 (ja) * 2019-10-18 2025-03-06 株式会社ソシオネクスト 半導体集積回路装置
US20220359545A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with dielectric fin structures
US11778803B2 (en) 2021-09-29 2023-10-03 Advanced Micro Devices, Inc. Cross FET SRAM cell layout
US11881393B2 (en) 2021-09-29 2024-01-23 Advanced Micro Devices, Inc. Cross field effect transistor library cell architecture design
US12598741B2 (en) * 2023-01-30 2026-04-07 Arm Limited Multi-stack bitcell architecture
US12580033B2 (en) * 2023-07-03 2026-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Read-only memory method, layout, and device
WO2026009666A1 (ja) * 2024-07-04 2026-01-08 株式会社ソシオネクスト 半導体記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054707A (ja) * 2007-08-24 2009-03-12 Renesas Technology Corp 半導体記憶装置およびその製造方法
JP4751432B2 (ja) * 2008-09-26 2011-08-17 シャープ株式会社 半導体記憶装置
US9400862B2 (en) * 2014-06-23 2016-07-26 Synopsys, Inc. Cells having transistors and interconnects including nanowires or 2D material strips
US9941290B2 (en) * 2016-06-01 2018-04-10 Taiwan Semiconductor Manufacaturing Co., Ltd. Read-only memory (ROM) device structure and method for forming the same
US10381100B2 (en) * 2016-07-01 2019-08-13 Synopsys, Inc. Enhancing memory yield and performance through utilizing nanowire self-heating
CN109390021B (zh) * 2017-08-03 2022-05-03 联华电子股份有限公司 只读存储器
SG11202005030XA (en) * 2017-11-28 2020-06-29 Univ Texas Catalyst influenced pattern transfer technology
US10833078B2 (en) * 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
JP7197505B2 (ja) * 2017-12-12 2022-12-27 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びその製造方法
WO2019220983A1 (ja) 2018-05-17 2019-11-21 株式会社ソシオネクスト 半導体集積回路装置
US11355504B2 (en) * 2018-05-31 2022-06-07 Intel Corporation Anti-ferroelectric capacitor memory cell
US11139300B2 (en) * 2019-11-20 2021-10-05 Intel Corporation Three-dimensional memory arrays with layer selector transistors

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