JPWO2020255656A5 - - Google Patents

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JPWO2020255656A5
JPWO2020255656A5 JP2021527512A JP2021527512A JPWO2020255656A5 JP WO2020255656 A5 JPWO2020255656 A5 JP WO2020255656A5 JP 2021527512 A JP2021527512 A JP 2021527512A JP 2021527512 A JP2021527512 A JP 2021527512A JP WO2020255656 A5 JPWO2020255656 A5 JP WO2020255656A5
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Japan
Prior art keywords
transistor
dimensional structure
transistors
node
storage device
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JP2021527512A
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English (en)
Japanese (ja)
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JPWO2020255656A1 (https=
JP7590656B2 (ja
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Priority claimed from PCT/JP2020/020978 external-priority patent/WO2020255656A1/ja
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Publication of JPWO2020255656A5 publication Critical patent/JPWO2020255656A5/ja
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JP2021527512A 2019-06-21 2020-05-27 半導体記憶装置 Active JP7590656B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019115211 2019-06-21
JP2019115211 2019-06-21
PCT/JP2020/020978 WO2020255656A1 (ja) 2019-06-21 2020-05-27 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPWO2020255656A1 JPWO2020255656A1 (https=) 2020-12-24
JPWO2020255656A5 true JPWO2020255656A5 (https=) 2022-03-16
JP7590656B2 JP7590656B2 (ja) 2024-11-27

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ID=74037253

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JP2021527512A Active JP7590656B2 (ja) 2019-06-21 2020-05-27 半導体記憶装置

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US (1) US12213298B2 (https=)
JP (1) JP7590656B2 (https=)
WO (1) WO2020255656A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7590655B2 (ja) * 2019-06-21 2024-11-27 株式会社ソシオネクスト 半導体記憶装置
CN116250077B (zh) * 2020-11-24 2025-08-22 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法
US12402293B2 (en) * 2022-09-23 2025-08-26 Apple Inc. Stacked SRAM cell architecture
WO2025062483A1 (ja) * 2023-09-19 2025-03-27 株式会社ソシオネクスト 半導体集積回路装置
US20260100206A1 (en) * 2024-10-07 2026-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with embedded power structure and methods of manufacturing thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2665644B2 (ja) * 1992-08-11 1997-10-22 三菱電機株式会社 半導体記憶装置
US8625334B2 (en) * 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
JP5726770B2 (ja) * 2012-01-12 2015-06-03 株式会社東芝 半導体装置及びその製造方法
JP2014222740A (ja) * 2013-05-14 2014-11-27 株式会社東芝 半導体記憶装置
JP5436731B1 (ja) * 2013-05-15 2014-03-05 三菱電機株式会社 数値制御加工プログラム作成装置
WO2014184933A1 (ja) * 2013-05-16 2014-11-20 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法
JP7402401B2 (ja) * 2018-09-05 2023-12-21 東京エレクトロン株式会社 モノリシック集積型３次元ｃｍｏｓロジック及びメモリを製造するためのアーキテクチャ設計及びプロセス

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