JPWO2021125138A1 - - Google Patents
Info
- Publication number
- JPWO2021125138A1 JPWO2021125138A1 JP2021565573A JP2021565573A JPWO2021125138A1 JP WO2021125138 A1 JPWO2021125138 A1 JP WO2021125138A1 JP 2021565573 A JP2021565573 A JP 2021565573A JP 2021565573 A JP2021565573 A JP 2021565573A JP WO2021125138 A1 JPWO2021125138 A1 JP WO2021125138A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/34—Source electrode or drain electrode programmed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
- H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
- H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019230713 | 2019-12-20 | ||
| JP2019230713 | 2019-12-20 | ||
| PCT/JP2020/046574 WO2021125138A1 (ja) | 2019-12-20 | 2020-12-14 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021125138A1 true JPWO2021125138A1 (https=) | 2021-06-24 |
| JPWO2021125138A5 JPWO2021125138A5 (https=) | 2022-08-15 |
| JP7610131B2 JP7610131B2 (ja) | 2025-01-08 |
Family
ID=76477544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021565573A Active JP7610131B2 (ja) | 2019-12-20 | 2020-12-14 | 半導体記憶装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US12279419B2 (https=) |
| JP (1) | JP7610131B2 (https=) |
| CN (1) | CN114868242B (https=) |
| WO (1) | WO2021125138A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7640861B2 (ja) * | 2019-10-18 | 2025-03-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US20220359545A1 (en) * | 2021-05-07 | 2022-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor memory devices with dielectric fin structures |
| US11778803B2 (en) | 2021-09-29 | 2023-10-03 | Advanced Micro Devices, Inc. | Cross FET SRAM cell layout |
| US11881393B2 (en) | 2021-09-29 | 2024-01-23 | Advanced Micro Devices, Inc. | Cross field effect transistor library cell architecture design |
| US12598741B2 (en) * | 2023-01-30 | 2026-04-07 | Arm Limited | Multi-stack bitcell architecture |
| US12580033B2 (en) * | 2023-07-03 | 2026-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Read-only memory method, layout, and device |
| WO2026009666A1 (ja) * | 2024-07-04 | 2026-01-08 | 株式会社ソシオネクスト | 半導体記憶装置 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160329313A1 (en) * | 2014-06-23 | 2016-11-10 | Synopsys, Inc. | Cells having transistors and interconnects including nanowires or 2d material strips |
| US20180233508A1 (en) * | 2016-06-01 | 2018-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Read-only memory (rom) device structure and method for forming the same |
| US20190172828A1 (en) * | 2017-12-04 | 2019-06-06 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
| WO2019108366A1 (en) * | 2017-11-28 | 2019-06-06 | Board Of Regents, The University Of Texas System | Catalyst influenced pattern transfer technology |
| WO2019116827A1 (ja) * | 2017-12-12 | 2019-06-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及びその製造方法 |
| WO2019220983A1 (ja) * | 2018-05-17 | 2019-11-21 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009054707A (ja) * | 2007-08-24 | 2009-03-12 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
| JP4751432B2 (ja) * | 2008-09-26 | 2011-08-17 | シャープ株式会社 | 半導体記憶装置 |
| US10381100B2 (en) * | 2016-07-01 | 2019-08-13 | Synopsys, Inc. | Enhancing memory yield and performance through utilizing nanowire self-heating |
| CN109390021B (zh) * | 2017-08-03 | 2022-05-03 | 联华电子股份有限公司 | 只读存储器 |
| US11355504B2 (en) * | 2018-05-31 | 2022-06-07 | Intel Corporation | Anti-ferroelectric capacitor memory cell |
| US11139300B2 (en) * | 2019-11-20 | 2021-10-05 | Intel Corporation | Three-dimensional memory arrays with layer selector transistors |
-
2020
- 2020-12-14 CN CN202080087274.2A patent/CN114868242B/zh active Active
- 2020-12-14 JP JP2021565573A patent/JP7610131B2/ja active Active
- 2020-12-14 WO PCT/JP2020/046574 patent/WO2021125138A1/ja not_active Ceased
-
2022
- 2022-06-16 US US17/842,473 patent/US12279419B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160329313A1 (en) * | 2014-06-23 | 2016-11-10 | Synopsys, Inc. | Cells having transistors and interconnects including nanowires or 2d material strips |
| US20180233508A1 (en) * | 2016-06-01 | 2018-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Read-only memory (rom) device structure and method for forming the same |
| WO2019108366A1 (en) * | 2017-11-28 | 2019-06-06 | Board Of Regents, The University Of Texas System | Catalyst influenced pattern transfer technology |
| US20190172828A1 (en) * | 2017-12-04 | 2019-06-06 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
| WO2019116827A1 (ja) * | 2017-12-12 | 2019-06-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及びその製造方法 |
| WO2019220983A1 (ja) * | 2018-05-17 | 2019-11-21 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114868242A (zh) | 2022-08-05 |
| CN114868242B (zh) | 2024-11-12 |
| WO2021125138A1 (ja) | 2021-06-24 |
| US20220310634A1 (en) | 2022-09-29 |
| JP7610131B2 (ja) | 2025-01-08 |
| US12279419B2 (en) | 2025-04-15 |
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